[fusheng-ji]

RFC #420 stack 7/10 (base test-h3, merge bottom-up): #483 → #484 → #485 → #486 → #487 → #488 → #489 → #493 → #494 → #586 → #587 → #588. This PR merges after #488; until the lower PRs merge, GitHub also shows their commits. This PR's own diff.

Evidence location: the measurement outputs of this PR (JSON, figures, audit files) are not part of its diff. They are on the fork's pr_assets branch under pr489/ (links in this description are fixed to that commit). Paths such as reports/experiments/... below name where a runner writes its output.

What

• norm_out as one autograd node:
  1. FP32 SiLU, then one cast to BF16;
  2. the deterministic tensor-core GEMV ([WS1][CUDA][MiniMax-H3] adaln_projection_3mod: three-modality AdaLN projection (RFC #420 stack 3/10) #485) on norm_out.linear, with shift taken first;
  3. the h3_rmsnorm kernel indexed by timestep_indices.
• The backward keeps the table gradient in FP32 all the way into the projection backward, so the parameter gradients pick up no extra BF16 rounding.
• The golden is FP64 and rounds only where the model stores a value in its own dtype: the SiLU cast, the BF16 norm_out.linear output, norm_out.norm's BF16 output and the BF16 1 + scale. All four are straight-through for the gradient.
• The e2e test now runs the whole conditioning path: timestep → MLP → projection → gather → block norm/modulation → gated residual → norm_out.

Prior art & reuse decision

Measured with tools/validation/models/h3_prior_art.py, committed in this stack. final_adaln_out.json was written from a clean tree at 6231a8c5 on an otherwise idle B200, and the operator doc's "Existing implementations" section has the figure and the command. Batch invariance is bitwise, for the forward, the per-row gradients and repeatability of every table and parameter gradient. It has three checks: every row computed alone vs inside full batches of 64, 257 and 2048 rows over three seeds; the full 131072-token batch vs sub-batches that together cover every row; and a dense batch-size sweep. Errors are max|err| / max|ref| against FP64; latency is the median forward + backward time. Libraries checked: diffusers, SGLang 0.5.21, Liger 0.8.4, Transformer Engine 2.20.2, vLLM 0.30.0 and Megatron-LM 52fbcbc (the training path of Miles and Vime); verl, Miles and Vime have no H3 diffusion operators.

Implementation	Batch-invariant	S = 4097: fwd err / worst grad err / fwd + bwd	S = 32768: fwd err / worst grad err / fwd + bwd
diffusers MiniMaxH3AdaLayerNormOut (op-for-op replay)	no (table / parameter gradients not repeatable)	8.3e-03 / 7.3e-02 / 1021 µs	8.9e-03 / 2.4e-01 / 4525 µs
rl-kernel H3FinalAdaLNOutCudaOp	yes	8.3e-03 / 5.2e-03 / 1642 µs	8.9e-03 / 5.7e-03 / 2959 µs

This stage adds no new kernel. It reuses #485's deterministic projection and #487's h3_rmsnorm kernel; the new code is the autograd node that connects them. The only candidate for reuse outside the stack is diffusers' own norm_out (MiniMaxH3AdaLayerNormOut). Its forward and per-row gradients are batch-invariant, but its parameter and temb gradients are not repeatable, because they go through index_select's atomic backward, and they are less accurate (temb 0.12, weight 0.24 at S = 32768, against 1.4e-3 and 3.8e-3 here). This stage is slower at S = 4097 (1.6 ms vs 1.0 ms forward + backward) and faster at S = 32768 (3.0 ms vs 4.5 ms). The batch-invariance checks for #485's and #487's kernels apply here unchanged.

Direct bitwise comparison (2026-10-13). There is no reuse candidate beyond diffusers' MiniMaxH3AdaLayerNormOut. This op does not promise bitwise equality: its shift/scale projection uses #485's fixed-order linear, not cuBLAS, so the output differs from diffusers in 0.06–0.07% of BF16 elements at every S from 1 to 32768, and every gradient differs as expected for the deterministic FP32 reductions.

Direct bitwise comparison

Measured with tools/validation/models/h3_bitwise_reuse.py (committed in #483, merged down the stack), which runs every candidate that h3_prior_art.candidates() defines on identical inputs, with each global batch-invariant mode in its own process, and compares every forward output and leaf gradient byte for byte with diffusers' path and with this kernel. final_adaln_out.json was written from a clean tree at 8cb4abed (python tools/validation/models/h3_bitwise_reuse.py --op final_adaln_out); the operator doc's "Direct bitwise comparison" section has the figure and the plot command.

Results (B200, B = 1, T = 3, pinned norm_out weights)

	RL-Kernel CUDA	diffusers
forward elements equal to diffusers	99.96%; the rest are projection 1-ULP ties	n/a
forward, S = 32768 / 131072	0.42 / 1.28 ms	0.82 / 2.96 ms
backward, S = 32768 / 131072	2.56 / 7.04 ms	4.47 / 17.7 ms
d_temb / dW / db error vs FP64	9.8e-4 / 3.1e-3 / 2.2e-3	4.3e-2 / 6.5e-2 / 5.3e-2 (varies run to run)
backward repeat-bitwise	yes	no

The whole-chain replay over T ∈ {1..4} × S ∈ {3, 257, 4097, 32768} finds that:

• all 7 stages are repeat-bitwise and within their contract tolerance;
• the 4 stages that promise bitwise equality with diffusers (sinusoid, gather, norm, gated residual) meet it in 16/16 cases each;
• every conditioning gradient is repeat-bitwise for the CUDA chain. Diffusers' is not repeat-bitwise for any S ≥ 257.

The data is in reports/experiments/h3-final-adaln-out-b200/{report,chain_replay}.json. report.json was regenerated 2026-10-26 from clean commit 1d26287f (pinned weights, backward-only timing); chain_replay.json is from clean commit a4bc99f9 (2026-10-13, after the golden fix) and has no timings. The report was measured on an otherwise idle B200.

Status

• Fixed: the goldens' declared cast, evidence regenerated (a4bc99f9, 7d716f22). NativeH3FinalAdaLNOutOp.forward_fp32, the test's _golden and the evidence report's backward golden rounded an FP64 SiLU for the declared BF16 cast; they now round the FP32 SiLU, as the model does (same fix as [WS1][CUDA][MiniMax-H3] adaln_projection_3mod: three-modality AdaLN projection (RFC #420 stack 3/10) #485's forward_fp32). report.json and chain_replay.json were regenerated from a clean tree at a4bc99f9 on an idle B200. The CUDA accuracy and every pass/fail flag are unchanged. In the chain replay, the h3_rmsnorm stage's error against the golden drops in all 16 cases (worst 0.0796 → 0.0671). Latencies were re-measured (below).

• Added: existing-implementation comparison, committed (tools/validation/models/h3_prior_art.py; report and figure for this op in reports/experiments/h3-prior-art-b200). Since 7203797 the branch gained only that runner, its evidence and the merges carrying them through the stack (no change outside docs/ and those scripts). See Prior art.

• Fixed: the BF16 gtest at larger S. Earlier revisions noted that --seq 257 missed a few gradient elements. The cause was the golden, not the kernel. Diffusers' norm_out stores norm_out.norm(x) and 1 + scale in BF16, and the golden computed both in FP64. 1 + scale is shared by every position of a timestep, so its missing rounding produced an error that grew with S. With both roundings declared straight-through (e4b8a62), the BF16 gtest passes at S = 257, 1024 and 4097. Before the fix, the CUDA candidate and the PyTorch reference missed the same elements. test_bf16_gradients_meet_gtest_contract fails on the old golden and passes on the new one.

• Open: the FP32 gtest at larger S. With every input in FP32, d_temb misses atol = rtol = 1e-4 from S = 257 and dW from S = 1024. Both are FP32 sums over 3·S rows, and the PyTorch reference misses the same gradients at the same S. H3 runs this op in BF16. Question for @Flink-ddd @inaniloquentee: should these long FP32 reductions accumulate in FP64? That changes the h3_det_linear kernels shared with [WS1][CUDA][MiniMax-H3] timestep_mlp_fp32: deterministic FP32 timestep MLP (RFC #420 stack 2/10) #484 and [WS1][CUDA][MiniMax-H3] adaln_projection_3mod: three-modality AdaLN projection (RFC #420 stack 3/10) #485. Or should the FP32 gradient tolerance scale with reduction length? The numbers are in the doc's Known Limitations.

• Merged [WS1][CUDA][MiniMax-H3] adaln_gate_residual: gated residual with in-kernel gate gather (RFC #420 stack 6/10) #488's latest state (7203797), carrying the review fixes of [WS1][CUDA][MiniMax-H3] adaln_projection_3mod: three-modality AdaLN projection (RFC #420 stack 3/10) #485–[WS1][CUDA][MiniMax-H3] adaln_gate_residual: gated residual with in-kernel gate gather (RFC #420 stack 6/10) #488. tests/models/minimax_h3 at 7203797 with two B200s visible: 418 passed, 1 skipped (matplotlib not installed), including the two-GPU device-validation tests. The evidence files were generated at e4b8a62; the merge changes no arithmetic of this op for non-empty inputs.

History

• 2026-10-26: backward timings regenerated. The final_adaln_out perf case had no backward setup, so its timed backward also ran the forward pass and built the graph (the guard test added for the gate-residual finding caught it). The case now prepares the graph before the timed call; report.json is rerun from a clean tree at 1d26287f with the pinned weights and the alternating execution order. Backward: 1.38 / 2.56 / 7.04 ms for S = 4097 / 32768 / 131072 (was 1.50 / 2.75 / 7.76 ms), diffusers 0.86 / 4.47 / 17.7 ms (was 1.07 / 5.34 / 20.8 ms). Accuracy is unchanged for the CUDA path; the diffusers errors vary run to run. The figure and report.json moved to the pr_assets commit named in the links above; chain_replay.json was not rerun (it has no timings). The H100 report was not rerun and still has the old backward timing.
• 2026-10-26: the stack is one ancestor chain. [WS1][CUDA][MiniMax-H3] timestep_sinusoid_h3: FP32 timestep features + shared H3 harness (RFC #420 stack 1/10) #483 → [WS1][CUDA][MiniMax-H3] timestep_mlp_fp32: deterministic FP32 timestep MLP (RFC #420 stack 2/10) #484 → … → [WS2][CUDA][MiniMax-H3] sp_norm_adaln: sequence-parallel norm/AdaLN/gated residual, byte-equal to WS1 (RFC #420 stack 9/10) #494 are merged forward in order (merge commits only, no force-push), so each branch contains its parent's head and merging the PRs in order does not conflict. All commits are signed off; GitHub's DCO check reports "could not be evaluated" on PRs above 250 commits ([WS2][CUDA][MiniMax-H3] tp_adaln_3mod: column-parallel AdaLN projection, byte-equal to WS1 (RFC #420 stack 8/10) #493, [WS2][CUDA][MiniMax-H3] sp_norm_adaln: sequence-parallel norm/AdaLN/gated residual, byte-equal to WS1 (RFC #420 stack 9/10) #494), which is an app limit, not a missing sign-off.
• 2026-10-23: history rewritten. Measurement outputs (JSON, figures, audit files) were removed from every branch and live on pr_assets (see the evidence note at the top), and all commits got a Signed-off-by trailer. Commit hashes in this body, including the clean-tree commit of the measurement, are the rewritten ones; the ZIPs and JSON files on pr_assets still carry the pre-rewrite hashes.
• 2026-10-13: fast-math guard (from the #483 review). KERNEL_ALIGN_USE_FAST_MATH=1 adds --use_fast_math to the whole _C build, which approximates expf/sinf/cosf/rsqrtf/division and flushes denormals. Before the fix a fast-math build of the top of the stack failed 33 H3 tests (the timestep_sinusoid_h3 and h3_rmsnorm bitwise tests and the chain/block tests built on them). nvcc 13 defines no fast-math macro, so the guard is in the build: every csrc/cuda/h3 source is listed in H3_BITWISE_SOURCES and left out of fast-math builds, the bindings are gated on KERNEL_ALIGN_WITH_H3_KERNELS, dispatch falls back to the PyTorch references, and tests that assert CUDA dispatch skip through require_h3_kernels. On this branch: merge 2a727086. Results for both builds are under Tests.
• 2026-10-10: repository refactor. Merged upstream test-h3@16b81175874e (notice): H3 CUDA code moved to rl_engine/backends/cuda/model_specific/minimax_h3, references to rl_engine/reference/minimax_h3, the harness to rl_engine/validation/models, with registration, build, tests, tools, docs and tools/migration/layout.json updated. Native arithmetic is unchanged; pinned evidence keeps its original commit metadata.
• Earlier test runs, superseded by Tests below: after the refactor merge (2× B200): 439 passed, 1 skipped; with the fast-math guard (2× B200, passed / skipped / failed): default 426 / 35 / 0, fast-math 149 / 312 / 0.

Pre-refactor validation (historical, before 2026-10-10)

python -m pytest tests/models/minimax_h3 -v
for s in 257 1024 4097; do
  python tools/validation/operators/check_operator.py --op final_adaln_out --candidate cuda --device cuda --dtype bf16 --batch 3 --seq $s --normalized-dim 5376 --check-grad
done
python tools/validation/models/h3_chain_replay.py --timesteps 1,2,3,4 --seq-lens 3,257,4097,32768 --backward --out chain_replay.json

Check	Result
tests/models/minimax_h3 at e4b8a62, one B200	195 passed, 11 skipped (all need two GPUs)
gtest BF16 --check-grad, S = 257 / 1024 / 4097, seed 123	passed; S = 257 and 4097 also pass at seeds 7 and 2026
gtest FP32 --check-grad	passes at S = 64; misses at S ≥ 257 as described in Status
Original implementation, full suite	3125 passed. The 19 failures and 1 collection error are all identical on unmodified test-h3.

The repository's CI workflows only run on PRs to main or test, so on test-h3 only the DCO and CodeRabbit checks run. The results above come from local runs on one B200.

Tests

Measured at commit de6a2245, an earlier head of this PR (later commits are listed under History and these runs were not repeated for the current head), 2× B200, pinned MiniMax-H3@42ed227 weights; each build compiled from a clean checkout of that commit:

python tools/weights/prepare_h3_weights.py --out <dir> && export RL_KERNEL_H3_WEIGHTS=<dir>
python setup.py build_ext --inplace                                  # default build
python -m pytest tests/models/minimax_h3 tests/build tests/runtime/test_dispatch.py -q
KERNEL_ALIGN_USE_FAST_MATH=1 python setup.py build_ext --inplace     # fast-math build, same pytest

Build	H3 kernels in _C	passed / skipped / failed
default	yes	458 / 3 / 0
KERNEL_ALIGN_USE_FAST_MATH=1	no (PyTorch reference fallback)	149 / 312 / 0

Default-build skips (environment only): 1 × could not import 'matplotlib'; 1 × could not import 'sglang.kernels.ops.diffusion.modulate.timestep_embedding_jit'; 1 × extension enforcement is CI-only (orchestrator sets RL_KERNEL_REQUIRE_EXT=1).

Fast-math regression tests: tests/build/test_build_platform_collectives.py::test_cuda_build_compiles_h3_kernels_without_fast_math, ::test_fast_math_build_excludes_bitwise_h3_kernels, tests/runtime/test_dispatch.py::test_h3_timestep_falls_back_when_fast_math_build_omits_kernel, ::test_h3_ops_prefer_cuda_and_fall_back_to_pytorch_reference.

On this PR the GitHub checks are DCO and CodeRabbit only (the CPU lint/unit/docs workflow for test-h3 arrives with #586), so the GPU results above are the test evidence.

Scope / Known limitations

CUDA only. The ROCm column stays open.

.coderabbit.yaml is not part of this operator. The branch carries the test-h3 CodeRabbit auto-review config, inherited through the stack from commits d113891 and 5c79216. The file is byte-identical to #490's, so it drops out of this diff once #490 merges into test-h3.

Summary by CodeRabbit

• New Features
  • Added MiniMax-H3 conditioning operations, including timestep features, projections, row gathering, RMSNorm with modulation, gated residuals, and final normalization.
  • Added CUDA implementations with PyTorch reference fallbacks on supported platforms.
  • Added deterministic forward and backward behavior for supported operations, plus validation for incompatible inputs.
  • Added tools to benchmark operations and compare accuracy, performance, and output consistency.
• Documentation
  • Added operator guides covering usage, supported backends, input requirements, and numerical behavior.

Results (H100 / Hopper)

Measured on 4 x NVIDIA H100 94GB (sm90, 95830 MiB reported), driver 580.173.02, CUDA 13.0, torch 2.13.0+cu130, pinned MiniMax-H3@42ed227, clean tree at 337ee604. Timing evidence was taken on an otherwise idle GPU. B200 and H100 are independent measurement sets (RFC #420); timings and raw bytes are not compared across GPUs. Evidence on pr_assets @ 5f14a845 under pr489/reports/experiments/*-head-337ee604-h100/.

Tests (pytest tests/models/minimax_h3 tests/build tests/runtime/test_dispatch.py)

• default build: 594 passed, 2 skipped
• KERNEL_ALIGN_USE_FAST_MATH=1 build: 170 passed, 426 skipped

Bitwise vs diffusers: matches B200 except one entry. final_adaln_out, case 1, forward out: bitwise equal on H100 (B200 had 4/5376 elements differing, max abs 7.8e-3). All other shared entries agree between the two GPUs.

Chain replay (h3_chain_replay.py --timesteps 1,2,3,4 --seq-lens 3,257,4097,32768 --backward): chain_replay.json. Candidate and candidate_fused backward paths are deterministic in every case; the provider backward is non-deterministic from S=257 upward.

Backward (H100): same protocol as #488 for final_adaln_out.

gradient	kernel repeatable	native diffusers repeatable	kernel error	native diffusers error	det diffusers error	kernel == det diffusers bitwise
x	yes	yes	5.3e-03	7.7e-03	7.7e-03	no
nw	yes	yes	7.0e-03	7.0e-03	7.0e-03	no
temb	yes	no	1.5e-03	4.4e-02	5.0e-02	no
w	yes	no	4.3e-03	9.2e-02	8.0e-02	no
b	yes	no	3.6e-03	7.2e-02	6.4e-02	no

Data: final_adaln_out-head-337ee604/.

Repeat check with 30 replays (native-repeat30-head-337ee604/final_adaln_out/): native diffusers gives 30 distinct results for temb, w and b (max relative spread up to 0.23 for w) at 32768 rows. Deterministic diffusers and the kernel give 1 distinct result for every gradient and size.

Diffusers-side fix: same RowGather harness link as #488 (https://github.com/fusheng-ji/RL-Kernel/tree/5f14a845b4f78adab2d1967a0017ec51f687029a/h3-backward-h100/rowgather-fix/REPORT.md).

For the gradients that go through the gather the kernel is about 10 to 30x more accurate than diffusers (native or deterministic): diffusers accumulates BF16 values in a fixed order, the kernel reduces in FP32 in a fixed tree. Element-wise and non-gather gradients are at the same rounding level as diffusers.

Figures

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Commits

Reviewing files that changed from the base of the PR and between 337ee60 and b58b112.

Files selected for processing: 45

• build_tools/extensions.py
• csrc/cuda/h3/adaln_row_gather.cu
• csrc/cuda/h3/det_linear.cu
• csrc/cuda/h3/gate_residual.cu
• csrc/cuda/h3/rmsnorm_modulate.cu
• csrc/cuda/h3/tile_metadata.cuh
• csrc/cuda/h3/timestep_sinusoid.cu
• docs/operators/h3-adaln-row-gather.md
• docs/operators/h3-final-adaln-out.md
• docs/operators/h3-timestep-mlp.md
• rl_engine/_C.pyi
• rl_engine/backends/cuda/model_specific/minimax_h3/adaln_modulation.py
• rl_engine/backends/cuda/model_specific/minimax_h3/adaln_projection.py
• rl_engine/backends/cuda/model_specific/minimax_h3/det_linear.py
• rl_engine/backends/cuda/model_specific/minimax_h3/final_adaln_out.py
• rl_engine/backends/cuda/model_specific/minimax_h3/gate_residual.py
• rl_engine/backends/cuda/model_specific/minimax_h3/rmsnorm.py
• rl_engine/backends/cuda/model_specific/minimax_h3/timestep_mlp.py
• rl_engine/backends/cuda/model_specific/minimax_h3/timestep_sinusoid.py
• rl_engine/reference/minimax_h3/__init__.py
• rl_engine/reference/minimax_h3/adaln_projection.py
• rl_engine/reference/minimax_h3/adaln_row_gather.py
• rl_engine/reference/minimax_h3/gate_residual.py
• rl_engine/reference/minimax_h3/rmsnorm.py
• rl_engine/reference/minimax_h3/timestep_mlp.py
• rl_engine/reference/minimax_h3/timestep_sinusoid.py
• rl_engine/validation/models/h3_chain.py
• tests/build/test_build_platform_collectives.py
• tests/models/minimax_h3/test_h3_adaln_gate_residual.py
• tests/models/minimax_h3/test_h3_adaln_modulation.py
• tests/models/minimax_h3/test_h3_adaln_projection.py
• tests/models/minimax_h3/test_h3_adaln_row_gather.py
• tests/models/minimax_h3/test_h3_assert_in_release_build.py
• tests/models/minimax_h3/test_h3_bitwise_reuse_plot.py
• tests/models/minimax_h3/test_h3_det_linear.py
• tests/models/minimax_h3/test_h3_det_linear_odd_width.py
• tests/models/minimax_h3/test_h3_final_adaln_out.py
• tests/models/minimax_h3/test_h3_report_timing.py
• tests/models/minimax_h3/test_h3_rmsnorm.py
• tests/models/minimax_h3/test_h3_rmsnorm_native_validation.py
• tests/models/minimax_h3/test_h3_timestep_mlp.py
• tests/models/minimax_h3/test_h3_timestep_sinusoid.py
• tests/runtime/test_dispatch.py
• tools/validation/models/h3_bitwise_reuse.py
• tools/validation/models/plot_h3_bitwise_reuse.py

Walkthrough

Adds MiniMax-H3 PyTorch references and CUDA operators for conditioning operations, including deterministic forward and backward paths. The changes register the operators for runtime dispatch and add operator tests, documentation, benchmarks, weight handling, and tools for replaying and comparing results.

Changes: MiniMax-H3 Conditioning

Layer / File(s)	Summary
Reference contracts and operators rl_engine/reference/minimax_h3/*, rl_engine/validation/models/h3_cases.py, rl_engine/validation/models/h3_provider.py, rl_engine/validation/models/h3_manifest.json, rl_engine/validation/models/h3_weights.py	Adds PyTorch reference operations, shared dimensions, fixed-order reductions, provider-path operations, deterministic input helpers, and manifest-validated weight loading.
Native CUDA kernels and extension bindings csrc/cuda/h3/*, csrc/bindings/ops.cpp, build_tools/extensions.py, rl_engine/_C.pyi	Adds CUDA implementations and bindings for sinusoid features, deterministic linear operations, AdaLN row gathering, RMSNorm modulation, and gated residuals. Build configuration omits H3 kernels when relaxed FP32 math is enabled.
CUDA operators and runtime dispatch rl_engine/backends/cuda/model_specific/minimax_h3/*, rl_engine/runtime/registry.py, rl_engine/validation/operators/operator_inputs.py, rl_engine/validation/operators/operator_specs.py	Adds Python CUDA wrappers and autograd paths, registers H3 operator priorities, and adds H3 operator input builders and specifications.
Replay, evidence, and benchmark tools rl_engine/validation/models/h3_chain.py, rl_engine/validation/models/h3_report.py, tools/validation/models/*, tools/weights/prepare_h3_weights.py, benchmarks/models/benchmark_h3_conditioning.py, tools/migration/*	Adds conditioning-chain replay, accuracy and performance reporting, comparison and plotting tools, benchmark entry points, pinned-weight preparation, and migration mappings.
Tests and operator documentation tests/models/minimax_h3/*, tests/build/test_build_platform_collectives.py, tests/runtime/test_dispatch.py, tests/validation/operators/test_ws1_gtest_gpu.py, docs/operators/*h3*, docs/operators/README.md, docs/.nav.yml	Adds operator, dispatch, build, timing, and validation tests. Adds operator documentation and navigation entries.

Priority: Normal

Estimated code review effort: 5 (Critical) | ~120 minutes

Sequence Diagram(s)

sequenceDiagram
  participant KernelRegistry
  participant H3CudaOperator
  participant PyBindH3Ops
  participant H3CudaKernels
  KernelRegistry->>H3CudaOperator: select CUDA backend
  H3CudaOperator->>PyBindH3Ops: invoke H3 operation
  PyBindH3Ops->>H3CudaKernels: launch CUDA kernel

Loading

Possibly related issues

• RL-Align/RL-Kernel issue 420 describes the MiniMax-H3 CUDA stage that includes the final AdaLN output projection and normalization. This change adds the final AdaLN output operator and its reference, CUDA, dispatch, and validation paths.

Merge Risk: Low · previous review 337ee

No merge-blocking defect remains. Before merging, fix the relaxed-math flag detection, the missing SM80 check in the final AdaLN op and the report's handling of partial reference failures. Align the final_adaln_out gradient-error golden with the registered golden so the published accuracy numbers are comparable.

Security Architecture Review

Security architecture risk: 🟡 Moderate · up to a236e

The new native operator surface does not consistently enforce metadata bounds and device ownership before accessing GPU memory. Normal gather calls validate their inputs, limiting exposure, but direct calls and the final-output path leave gaps. No remote exploit, privilege escalation, or cross-tenant access was established.

Retained concerns

• Medium · security · inferred: Metadata validation is not consistently enforced across the new native boundary. Direct gather calls can supply out-of-range row or reduction metadata that kernels dereference without bounds checks. Default gather wrappers validate values, and the documented unchecked mode requires prevalidation. Nevertheless, the final-output public path also omits index-device equality, unlike the existing modulation validator, and native RMSNorm does not restore that requirement. Malformed or cross-device metadata can therefore reach GPU pointer access, potentially exposing process-local memory or causing a CUDA fault. Reachability requires control of tensor arguments or an unchecked call path; remote reachability and wider isolation failures are not established.

Security review details

Security Blast Radius

• inferred — The evidenced native-memory exposure is bounded to callers supplying tensors to the Python/CUDA operator surface and the address space accessible to its GPU execution context. Broader tenant, service, credential or environment exposure cannot be inferred without deployment and caller-trust context.

Security Findings and Attack Paths

• inferred — A caller controlling an unchecked gather invocation can supply invalid indices that become native row offsets and GPU reads. Backward similarly trusts caller-supplied segment metadata. This supports a potential process-local disclosure or fault path, not demonstrated exploitation. The default registered gather path rejects invalid values before dispatch.

Trust Boundaries and Controls

• observed — Gather safety normally depends on Python validation; disabling range checks is explicitly documented for prevalidated indices. In contrast, the new final-output validator checks index values but omits device equality, and the native modulation constructor checks CUDA placement without matching the index device to the activation device.

Resilience and Maintainability Implications

• inferred — The extracted-weight workflow delegates integrity after preparation to the selected local directory. Same-schema replacement or stale output is not detected by the loader, but the inspected consumers are tests and replay/report tooling, and no attacker-controlled filesystem boundary was established.

Hardening Proposals

• proposed — Separate checked public entrypoints from explicitly trusted fast paths, and consistently enforce metadata bounds and launch-device ownership at the checked native boundary.
• proposed — If extracted weights must remain authoritative across shared-cache use or reruns, publish them atomically and bind consumer acceptance to content provenance. Otherwise, explicitly document the trusted-local-file assumption.

Pre-merge checks: 4 · 1

Failed checks: 1 inconclusive

Check name	Status	Explanation	Resolution
Docstring Coverage		Docstring coverage is 26.73% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 752 functions across 94 files. (33 skippe…	Write docstrings for the functions missing them to satisfy the coverage threshold.

Passed checks: 4 passed

Check name	Status	Explanation
Title check		The title clearly identifies the primary MiniMax-H3 change: final AdaLN output projection combined with final normalization and modulation. The RFC stack context is additional but relevant.
Linked Issues check		Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check		Check skipped because no linked issues were found for this pull request.
Description Check		Check skipped - CodeRabbit’s high-level summary is enabled.

Full details: Docstring Coverage

Explanation

Docstring coverage is 26.73% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 752 functions across 94 files. (33 skipped: 12 unsupported, 21 over the file limit.)

Resolution

Write docstrings for the functions missing them to satisfy the coverage threshold.

Finishing Touches: 💡 1

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Actionable comments posted: 2

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Inline comments:
Review comments at @csrc/cuda/h3/rmsnorm_modulate.cu:
- Around line 279-280: Add device-equality checks against x.device() at the
native boundary: update make_modulation to validate ix, check_xw to validate
weight, and the rstd validation in h3_rmsnorm_backward. Keep the existing dtype,
shape, and contiguity checks intact.

Review comments at @rl_engine/testing/h3_report.py:
- Around line 637-642: Update the grads helper and final_adaln_out reference
path to compute golden gradients with FP64 leaves and gradient input, while
explicitly preserving the declared BF16 quantization boundaries in the forward
computation instead of relying on golden_op.forward_fp32 with FP64 weights.
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📥 Commits

Reviewing files that changed from the base of the PR and between 32b765e and a236ef4.

⛔ Files ignored due to path filters (7)

• docs/usage/evidence/h3-adaln-gate-residual-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-adaln-projection-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-adaln-row-gather-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-final-adaln-out-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-rmsnorm-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-timestep-mlp-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-timestep-sinusoid-b200/figure.png is excluded by !**/*.png

📒 Files selected for processing (72)

• benchmarks/benchmark_h3_conditioning.py
• csrc/cuda/h3/adaln_row_gather.cu
• csrc/cuda/h3/det_linear.cu
• csrc/cuda/h3/gate_residual.cu
• csrc/cuda/h3/rmsnorm_modulate.cu
• csrc/cuda/h3/timestep_sinusoid.cu
• csrc/ops.cpp
• docs/.nav.yml
• docs/operators/README.md
• docs/operators/h3-adaln-gate-residual.md
• docs/operators/h3-adaln-projection.md
• docs/operators/h3-adaln-row-gather.md
• docs/operators/h3-final-adaln-out.md
• docs/operators/h3-rmsnorm.md
• docs/operators/h3-timestep-mlp.md
• docs/operators/h3-timestep-sinusoid.md
• docs/usage/evidence/h3-adaln-gate-residual-b200/report.json
• docs/usage/evidence/h3-adaln-projection-b200/report.json
• docs/usage/evidence/h3-adaln-row-gather-b200/chain_replay.json
• docs/usage/evidence/h3-adaln-row-gather-b200/report.json
• docs/usage/evidence/h3-final-adaln-out-b200/chain_replay.json
• docs/usage/evidence/h3-final-adaln-out-b200/report.json
• docs/usage/evidence/h3-rmsnorm-b200/report.json
• docs/usage/evidence/h3-timestep-mlp-b200/report.json
• docs/usage/evidence/h3-timestep-sinusoid-b200/report.json
• rl_engine/_C.pyi
• rl_engine/kernels/gtest/operator_inputs.py
• rl_engine/kernels/gtest/operator_specs.py
• rl_engine/kernels/ops/cuda/h3/__init__.py
• rl_engine/kernels/ops/cuda/h3/adaln_modulation.py
• rl_engine/kernels/ops/cuda/h3/adaln_projection.py
• rl_engine/kernels/ops/cuda/h3/adaln_row_gather.py
• rl_engine/kernels/ops/cuda/h3/det_linear.py
• rl_engine/kernels/ops/cuda/h3/final_adaln_out.py
• rl_engine/kernels/ops/cuda/h3/gate_residual.py
• rl_engine/kernels/ops/cuda/h3/rmsnorm.py
• rl_engine/kernels/ops/cuda/h3/timestep_mlp.py
• rl_engine/kernels/ops/cuda/h3/timestep_sinusoid.py
• rl_engine/kernels/ops/pytorch/h3/__init__.py
• rl_engine/kernels/ops/pytorch/h3/adaln_projection.py
• rl_engine/kernels/ops/pytorch/h3/adaln_row_gather.py
• rl_engine/kernels/ops/pytorch/h3/final_adaln_out.py
• rl_engine/kernels/ops/pytorch/h3/fixed_order.py
• rl_engine/kernels/ops/pytorch/h3/gate_residual.py
• rl_engine/kernels/ops/pytorch/h3/rmsnorm.py
• rl_engine/kernels/ops/pytorch/h3/timestep_mlp.py
• rl_engine/kernels/ops/pytorch/h3/timestep_sinusoid.py
• rl_engine/kernels/registry.py
• rl_engine/testing/h3_cases.py
• rl_engine/testing/h3_chain.py
• rl_engine/testing/h3_manifest.json
• rl_engine/testing/h3_provider.py
• rl_engine/testing/h3_report.py
• rl_engine/testing/h3_weights.py
• rl_engine/tests/test_dispatch.py
• scripts/h3_chain_replay.py
• scripts/h3_evidence.py
• scripts/plot_h3_evidence.py
• scripts/prepare_h3_weights.py
• setup.py
• tests/h3/conftest.py
• tests/h3/test_h3_adaln_gate_residual.py
• tests/h3/test_h3_adaln_modulation.py
• tests/h3/test_h3_adaln_projection.py
• tests/h3/test_h3_adaln_row_gather.py
• tests/h3/test_h3_conditioning_e2e.py
• tests/h3/test_h3_final_adaln_out.py
• tests/h3/test_h3_rmsnorm.py
• tests/h3/test_h3_timestep_mlp.py
• tests/h3/test_h3_timestep_sinusoid.py
• tests/h3/test_prepare_h3_weights.py
• tests/test_ws1_gtest_gpu.py

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[github-actions]

The host enforces only K % (16/sizeof(T)) == 0 (8 for BF16), but the MMA forward loads a 16-byte chunk at k = kb + 32*u + 8*q and the load guard is k < k_in. For BF16 with K % 8 == 0 but K % 32 in {8, 16, 24}, the last step can start a load at k = K - 8 (in bounds for 8 elements) while the second mma.sync group consumes k + 4 .. k + 7 — still inside the row — but a_lo[u].y/.w and bx[u].y/.w (elements k+2..k+3, k+6..k+7) are read from a 16-byte vector whose elements 8..15 then belong to the next row's data. Because the accumulator of that second mma is added unconditionally (the break only checks kb + 32*u >= k_in), products whose k indices exceed K are summed into acc, producing a wrong result (not an out-of-bounds read, since the row is padded by the neighboring row). Constrain the MMA path to K % 32 == 0 (or mask per-quad), and keep the looser K % vec == 0 check only for the FP32 kernel.

[fusheng-ji]

Not changed. The host requires K % vec == 0 (vec = 16 / sizeof(T): 8 for BF16, 4 for FP32), and the forward MMA kernel loads the 16-byte chunk at k = kb + 32u + 8q only when k < K; with K % 8 == 0 that already means k + 8 <= K, so no chunk straddles the end of a row, and a quad whose k is past K is zero-filled (zero), which adds +0.0f to the accumulator. The finding's own walk-through ends with "not an out-of-bounds read, since the row is padded by the neighboring row", but there is no such padding to read: elements 8..15 of a 16-byte chunk are never loaded, because every chunk is exactly the eight elements [k, k+8) of its row. Requiring K % 32 == 0 would reject shapes the kernel supports (the sweep below has BF16 K = 8, 24, 40, 72, 264, 520, 1032) without removing a hazard. Checked, not argued: the forward, input-gradient and weight-gradient kernels with BF16 K in {8, 24, 40, 72, 264, 520, 1032} and FP32 K in {4, 12, 20, 36, 132, 1044}, N in {1, 3, 17, 33}, rows in {1, 3, 5} ran (previous round) under compute-sanitizer --tool memcheck with 0 errors and 0 mismatches against an FP64 golden, and the contract header documents the invariant at the loads.

[github-actions]

The branch is inverted: if (mod.index != nullptr) dereferences mod.shift/mod.scale, which are only set when an index is provided. When mod.index == nullptr (the unmodulated path, which make_modulation explicitly supports and h3_rmsnorm_backward still uses in rmsnorm_modulate_dx_kernel), this branch is skipped, so shift/scale stay nullptr — fine here. But the modulated path then modulation_row(mod, r) uses mod.index[r % mod.seq] while the null-check chosen here is on index; since mod.shift/mod.scale are non-null exactly when mod.index != nullptr, this is consistent... The real defect is in rmsnorm_modulate_dx_kernel: it computes scale via modulation_row(mod, r) where modulation_row reads mod.index[r % mod.seq] and asserts range — however mod.seq defaults to 1 when make_modulation returns the empty default struct (no index), and mod.rows stays 0, so CUDA_KERNEL_ASSERT(i >= 0 && i < 0) would fire. In that early-return path mod.index is nullptr so modulation_row is not called there either. Still, mod.seq/mod.rows are initialized to 1, 0 rather than 0, 0, and any future caller checking mod.seq before mod.index would divide by modulo of a stale value; please initialize seq = 0 (or make the empty struct self-consistent).

[fusheng-ji]

Not changed: the branch is not inverted. index != nullptr is the modulated path and is where shift/scale are set (make_modulation fills them together with index); with no index they stay nullptr and the unmodulated rows skip the branch, which is what the plain norm and h3_rmsnorm_backward without a table use. The finding walks through the cases itself and finds them consistent. On the remaining suggestion: the empty struct's seq = 1 is deliberate, because r % seq with seq = 0 is undefined behaviour, while r % 1 is defined for any code that computes it before looking at the index; 5601118 says so in a comment at the initialiser.

[github-actions]

The row-gather backward here is called with torch.float32 as the output dtype, but the table produced by det_linear_forward is in weight.dtype (BF16 in practice). If the native backward honors the requested dtype (as the standalone adaln_row_gather._H3AdaLNRowGatherCuda.backward assumes when it passes rows_dtype), d_rows is FP32 and d_table stays FP32, which is the intended contract — but this only holds if the kernel truly writes FP32 regardless of the rows dtype. Please confirm the kernel writes rows_dtype (not the input gradient dtype); otherwise d_table.view(num_timesteps, width) is a reinterpretation of a different-dtype buffer and the downstream det_linear_backward_weight feed is corrupted.

[fusheng-ji]

Not changed, confirmed. The native backward allocates {num_rows, chunks * hidden} in the out_dtype it is given (grad.options().dtype(out_dtype) in adaln_row_gather.cu) and dispatches the fold on that dtype, whatever the dtype of the incoming gradient. This call passes torch.float32, so d_rows and d_table are FP32 even though grad_packed and the table are in the weight dtype, and det_linear_backward_weight takes FP32 gradients. test_backward_writes_the_requested_dtype_whatever_the_gradient_dtype (65e8620) pins it for FP32, BF16 and FP16 gradients and both output dtypes, and test_backward_keeps_table_gradient_fp32 pins the fused path.

[github-actions]

The tokenizer re-splits every shlex word on whitespace and ;, which breaks shell quoting for a path or file name that legitimately contains a space or ;. With NVCC_APPEND_FLAGS='--options-file "my opts.txt"' (or -optf "a;b.txt"), words becomes ['--options-file', 'my', 'opts.txt'], so the value is taken as my, the read fails, and _UncheckableFlags silently drops the H3 kernels from a valid build. Worse, if a file literally named my happens to exist in cwd, its content is parsed instead of the real options file, so real relaxed-math flags in my opts.txt are never seen — a fail-open path in the predicate that is supposed to guarantee bitwise parity. Splitting only the shlex word itself (not its quoted contents) or handling ; before shlex would preserve quoted values.

[fusheng-ji]

Fixed in 562d3fa (#483, where build_tools/extensions.py lives; this PR contains it). Checked against nvcc 13.0 with --dryrun: it honours double quotes (NVCC_APPEND_FLAGS='--options-file "my opts.txt"' opens my opts.txt), does not treat single quotes or a backslash as quoting (it then fails to open 'my), and does not split on ; (--use_fast_math;-g is an unknown option). The tokenizer now follows that: ; separates words outside quotes only, and a quoted word stays whole for a file name. A quoted word that contains whitespace or ; is also scanned piece by piece for relaxed flags, so "-O2 --use_fast_math" still reads as relaxed. The fail-open you describe reproduced on the old code: with a file my next to my opts.txt, the predicate read my, saw no flag and returned None; it now returns NVCC_APPEND_FLAGS contains --use_fast_math. Tests use both files as decoys, for --options-file "...", -optf="..." and a name with ;, and the nvcc --dryrun oracle covers the quoted spellings.

[github-actions]

_tokens_relax_math fails open on a value flag whose spelling nvcc rejects or reinterprets. --ftz=1 is handled only because 1 is listed, but --ftz=yes, --prec-div=maybe, or --prec-div=FALSE (uppercase is fine via .lower(), but --prec-div=no) fall through value.lower() in relaxed_values and return None, so _relaxed_math_reason() reports nothing and the H3 kernels are compiled with the define while an options string that relaxes (or that nvcc will reject) is in effect. The docstring of _relaxed_math_reason promises to fail closed on values it cannot parse; anything that is neither the safe spelling (false/true per flag) nor the relaxed set should be reported as uncheckable rather than treated as safe.

Suggestion:

Suggested change

	if value.lower() in relaxed_values:
	return spelled
	return None
	if value.lower() in relaxed_values:
	return spelled
	if value.lower() not in _SAFE_RELAXED_MATH_VALUES[name]:
	return f"{spelled} (unrecognised value)"
	return None

[fusheng-ji]

Fixed in 562d3fa. A value of --ftz / --prec-div / --prec-sqrt that is neither the relaxed spelling nor the exact one (false / true / true) is now reported (... contains --ftz=yes (a value nvcc does not take)), so the H3 kernels are left out of such a build instead of being kept on the strength of a flag nobody parsed. nvcc itself stops on those values, so no such build compiled with them, but the predicate no longer reads them as safe. Upper-case spellings of the real values (--ftz=FALSE) are still read as exact. --prec-div=no and the others are in the new test_values_nvcc_does_not_take_are_not_read_as_the_exact_spelling.

[github-actions]

can_vectorize and the vector branch handle only n / kVecElems full chunks; there is no scalar tail for n % kVecElems != 0. The guard checks n % vec != 0 with vec = 16 / gate.element_size(), which for FP32 (vec = 4) admits n = 4 (fine) but the same expression also admits e.g. n = 12? — no, 12 % 4 == 0. The actual defect is for FP16: vec = 16 / 2 = 8, and n = 8 passes; but kVecElems for T = __half is 16 / sizeof(__half) = 8 as well, so the chunk count matches. Still, the residual n % kVecElems elements are never written whenever the vectorized path is chosen with a non-multiple n, which the n % vec check does not prevent when gate.element_size() differs from sizeof(T) — verify that gate.element_size() == sizeof(T) for all dispatched types and, if not guaranteed, mask the tail. As written the row is out + r * n with n not chunk-aligned, so reinterpret_cast<const uint4*>(ar)[v] also assumes 16-byte alignment of every row start, which requires n * elem % 16 == 0; add that to can_vectorize since only gate.stride(0) alignment is checked today.

[fusheng-ji]

Not changed; the vector path has no tail and every row start is aligned. make_gate requires the gate to have the activations' dtype, so 16 / gate.element_size() is kVecElems for T, and can_vectorize requires n % vec == 0: the n / kVecElems chunks cover each row exactly, and a row starts at r * n * sizeof(T), a multiple of 16 bytes once the base pointers are 16-byte aligned (also checked: the gate, residual, y and out data pointers and stride(0) * element_size() % 16). Anything else takes the scalar path, which is tested with odd widths and sliced gate views.

[github-actions]

rmsnorm_modulate_dx_kernel writes dx for every j in [0, n), but the loop iterates only over n / kVec full vectors (for (int i = thrx; i < n / kVec; i += numx)). check_xw enforces n % kVec == 0, so the loop does cover the whole row — but the same pattern is used for the forward, so this is consistent. The real problem is in the modulation gradient: modulation_grad_partial_kernel writes partial[tile * 2 * n + j2] with j2 < 2 * n, and fold_segments_kernel folds with width = 2 * n. That matches. The mismatch to fix is that table_grad is indexed seg * width with segments == gate.size(0) while seg_first_tile has segments + 1 entries built by the caller from shift->size(0); make_modulation requires sh.size(0) == sc.size(0) but the backward then indexes d_shift/d_scale as narrow(1, 0, n) / narrow(1, n, n) on a (segments, 2n) buffer — consistent. No change needed here; verifying only.

[fusheng-ji]

Not changed; the finding says "No change needed here; verifying only".

[github-actions]

The relaxed-math gate inspects only NVCC_PREPEND_FLAGS/NVCC_APPEND_FLAGS/TORCH_NVCC_FLAGS, but PyTorch's BuildExtension does not use all of them the same way. In particular TORCH_NVCC_FLAGS is only consumed when torch.utils.cpp_extension falls into its _get_cuda_arch_flags-less path (no NVCC_APPEND_FLAGS); and torch also honours NVCC_PREPEND_FLAGS/NVCC_APPEND_FLAGS plus the flags in os.environ['NVCC_FLAGS']-adjacent paths and CUDA_HOME-derived nvcc wrappers. More importantly, the predicate never sees -Xcompiler/nvcc flags that reach the compiler via TORCH_CUDA_ARCH_LIST-style options files or via the CC/CXX/NVCC wrapper scripts. If any of those paths introduces --use_fast_math/--ftz=true, neither this function nor the docs' claim that the extension "is built without --use_fast_math" holds: h3_enabled stays True and the H3 kernels are compiled with relaxed math while their bindings are exported. Since nvcc exposes no in-source macro, there is no second line of defence.

If the intent is to cover exactly these three variables, that contract should be stated (and documented) rather than implied; additionally TORCH_NVCC_FLAGS should be checked with the separator torch actually uses (;), which _nvcc_flag_words does globally, so a TORCH_NVCC_FLAGS='-optf a.opts;b.opts' is read as two separate words rather than one comma list — worth confirming against torch's parsing.

[fusheng-ji]

Not changed. nvcc does not read CFLAGS, CXXFLAGS or CPPFLAGS: with all three set to --use_fast_math --ftz=true --prec-div=false, nvcc --dryrun on a division kernel prints none of those options, same as with no variables set (checked with nvcc 13.0). The channels it does read are NVCC_PREPEND_FLAGS, NVCC_APPEND_FLAGS and, through the torch build, TORCH_NVCC_FLAGS; _relaxed_math_reason() covers those, including --options-file/-optf files named in them. -Xcompiler, -Xptxas and -Xcudafe pass options to the host compiler, ptxas and the front end and do not change -ftz or -prec-div, which are cicc options. The ; separator of TORCH_NVCC_FLAGS is handled by the lexer (; is a separator, quoted words stay whole) and the tests added in 562d3fa3 cover it.

[github-actions]

weight/bias are never checked to live on the same CUDA device as temb. _validate_indices builds its stand-in tensor on temb.device, and the dtype cast act = F.silu(temb).to(weight.dtype) moves the activation onto weight.device, so a mismatched weight (different GPU) would silently launch the projection on a different device than the indices validation checked, or crash at the extension boundary. Add an explicit weight.device == temb.device / bias.device == temb.device guard (or rely on a shared validator) before the autograd call.

[fusheng-ji]

Not changed. The activation act = F.silu(temb).to(weight.dtype) stays on temb's device (.to(dtype) does not move devices), and h3_det_linear_forward checks x and weight must be on the same device and bias and weight must be on the same device before launching, so a weight or bias on another GPU raises at the extension boundary. _validate_indices builds its stand-in on temb.device (the fix from the previous round), so the index check and the projection run on the same device.

[github-actions]

_segment_tiles(index, num_rows) uses num_rows as the minlength for torch.bincount and to build the seg_first_tile/tile_seg arrays, which are then passed to h3_adaln_row_gather_backward. h3_adaln_indices produces indices in [0, T*3) for the gather op (the projection table has T*3 rows of 6H). Using num_timesteps * H3_MODALITY_NUM here happens to match (index is the raw (T,M) modulation row), but the tiles are then paired with d_rows reshaped as (num_timesteps, width) where width = 18H, i.e. the backward input only has T table rows worth of data — confirm the kernel side (h3_adaln_row_gather_backward) interprets the tile row range as position ranges over grad_packed and not just densities over a table of T*3 rows, otherwise out-of-range/partial tile reads occur. Please add an assertion that d_rows.numel() == num_timesteps * width to catch a shape mismatch between the projection table and the gather output.

[fusheng-ji]

Not changed. _segment_tiles(index, num_timesteps * H3_MODALITY_NUM) describes the rows of the gather table (T * 3), the same num_rows the forward used, and d_rows has T * 3 rows by construction: h3_adaln_row_gather_backward allocates {num_rows, width} from the tile metadata and the gradient. The shape equals num_timesteps * width, and d_rows.view(num_timesteps, width) raises if it did not, so an numel() assertion would repeat the check view already makes. The tile pre-pass (in e366ecef) now also requires tiles to partition the positions in order.

[github-actions]

The SiLU VJP uses pre (pre-activation) saved from the native forward, while the native forward applies SiLU internally with activation=ACT_SILU. Confirm the extension stores the true FP32 pre-activation (not the post-SiLU hidden) in save_pre_activation; if it stores the activated value, the backward would compute s = sigmoid(hidden) which is numerically wrong yet still bitwise-stable, making it invisible to bitwise tests. Please cross-check h3_det_linear_forward's save_pre_activation semantics in csrc/cuda/h3/det_linear.cu.

[fusheng-ji]

Not changed; it stores the pre-activation. In the forward kernel pre_act[t * n_out + n] = v is written with v = sum + bias, and the SiLU is applied on the next line (v = v / (1.0f + expf(-v))). The backward uses that pre as z in the VJP. This is not invisible to bitwise tests: the MLP tests compare the input and weight gradients with an FP64 autograd of SiLU (_fp64_grads), which a post-activation pre would miss by far more than the tolerance.