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RFC #420 stack 2/10 (base test-h3, merge bottom-up): #483 → #484 → #485 → #486 → #487 → #488 → #489 → #493 → #494 → #586 → #587 → #588. This PR merges after #483; until the lower PRs merge, GitHub also shows their commits. This PR's own diff.

Evidence location: the measurement outputs of this PR (JSON, figures, audit files) are not part of its diff. They are on the fork's pr_assets branch under pr484/ (links in this description are fixed to that commit). Paths such as reports/experiments/... below name where a runner writes its output.

What

• New csrc/cuda/h3/det_linear.cu (contract h3-det-linear-v1): a GEMV whose summation order
  is fixed per output column. Because of that order:
  • each timestep's row is bitwise batch- and position-invariant;
  • every run is repeat-bitwise.
• The FP32 256→5376→2688 MLP, with SiLU fused into the first layer.
• A backward with no cuBLAS and no atomics:
  • dx comes from fixed-chunk ordered folds, so it is row-local;
  • dW and db come from ascending-row folds.
• BF16 inputs are rejected (probe H7), because time_embedder is a declared FP32 module.

Prior art & reuse decision

Measured with tools/validation/models/h3_prior_art.py, committed in this stack. timestep_mlp.json was written from a clean tree at 39f0f805 on an otherwise idle B200, and the operator doc's "Existing implementations" section has the figure and the command. Batch invariance is bitwise, for the forward, the per-row gradients and repeatability of every table and parameter gradient. It has three checks: every row computed alone vs inside full batches of 64, 257 and 2048 rows over three seeds; the full 4096-timestep batch vs sub-batches that together cover every row; and a dense batch-size sweep. Errors are max|err| / max|ref| against FP64; latency is the median forward + backward time. Libraries checked: diffusers, SGLang 0.5.21, Liger 0.8.4, Transformer Engine 2.20.2, vLLM 0.30.0 and Megatron-LM 52fbcbc (the training path of Miles and Vime); verl, Miles and Vime have no H3 diffusion operators.

Implementation	Batch-invariant	T = 3: fwd err / worst grad err / fwd + bwd	T = 256: fwd err / worst grad err / fwd + bwd	T = 2048: fwd err / worst grad err / fwd + bwd
diffusers TimestepEmbedding, FP32 F.linear [plain]	no (14214 rows differ; 4108 sub-batches differ)	5.7e-07 / 4.1e-07 / 777 µs	5.7e-07 / 1.0e-06 / 832 µs	3.7e-06 / 2.0e-06 / 3609 µs
rl-kernel H3TimestepMLPCudaOp	yes	2.6e-07 / 4.2e-07 / 748 µs	2.3e-07 / 7.6e-07 / 4595 µs	2.6e-07 / 2.3e-06 / 43.0 ms
diffusers TimestepEmbedding, FP32 F.linear [vllm]	no (14214 rows differ; 4096 sub-batches differ)	1.8e-07 / 4.5e-07 / 752 µs	3.7e-06 / 2.8e-06 / 921 µs	3.7e-06 / 3.2e-06 / 3826 µs
diffusers TimestepEmbedding, FP32 F.linear [sglang]	yes	1.6e-03 / 1.6e-03 / 1036 µs	1.5e-03 / 1.5e-03 / 1140 µs	1.5e-03 / 1.7e-03 / 2636 µs
diffusers TimestepEmbedding, FP32 F.linear [sglang_ieee]	yes	3.3e-06 / 2.3e-06 / 2234 µs	3.7e-06 / 2.8e-06 / 2428 µs	3.7e-06 / 3.2e-06 / 7329 µs
diffusers TimestepEmbedding, FP32 F.linear [megatron_te_native]	no (14214 rows differ; 4108 sub-batches differ)	1.8e-07 / 4.1e-07 / 729 µs	3.7e-06 / 1.0e-06 / 814 µs	3.7e-06 / 2.0e-06 / 3636 µs
diffusers TimestepEmbedding, FP32 F.linear [megatron_triton]	yes	1.6e-03 / 1.6e-03 / 1027 µs	1.5e-03 / 1.5e-03 / 1137 µs	1.5e-03 / 1.7e-03 / 2634 µs
diffusers TimestepEmbedding, FP32 F.linear [megatron_triton_ieee]	yes	3.3e-06 / 2.3e-06 / 2309 µs	3.7e-06 / 2.8e-06 / 2435 µs	3.7e-06 / 3.2e-06 / 7349 µs

An earlier version of this section said no batch-invariant FP32 implementation exists; that was wrong. SGLang's and Megatron's Triton batch-invariant modes make it batch-invariant, replacing aten::mm / addmm for the whole process, and with TRITON_F32_DEFAULT=ieee they keep FP32 accuracy (without it they run TF32, forward error 1.6e-3). At H3's T = 1–4 this kernel is about 3× faster than those modes (737–755 µs vs 2233–2309 µs forward + backward) and about 10× more accurate (forward error 2.4–2.6e-7 vs 2.5–3.3e-6). It is still faster at T = 64 (1.3 ms vs 2.3 ms), but slower from T = 256 (4.6 ms vs 2.4 ms) and at T = 2048 (43 ms vs 7.3 ms). cuBLAS on its own, vLLM's mode and Megatron's te_native mode are not batch-invariant here. Question for @Flink-ddd @inaniloquentee: keep the kernel, or use one of the Triton modes?

Direct bitwise check (2026-10-13). No mode reproduces this kernel's bits at any T: 90.6–100% of the FP32 outputs differ. None is a bitwise drop-in for diffusers at H3's T = 1–4 either. vLLM's settings and Megatron te_native match at T = 1 and T ≥ 64 but not at T = 4. SGLang/Megatron Triton with ieee match only from T = 64. The TF32 Triton modes never match. Whichever option is chosen therefore changes the numerics relative to both diffusers and this kernel, so the choice is about accuracy and speed, not parity.

Direct bitwise comparison

Measured with tools/validation/models/h3_bitwise_reuse.py (committed in #483, merged down the stack), which runs every candidate that h3_prior_art.candidates() defines on identical inputs, with each global batch-invariant mode in its own process, and compares every forward output and leaf gradient byte for byte with diffusers' path and with this kernel. timestep_mlp.json was written from a clean tree at 73939f2d (python tools/validation/models/h3_bitwise_reuse.py --op timestep_mlp --megatron-src <Megatron-LM tree>); the operator doc's "Direct bitwise comparison" section has the figure and the plot command. B200, torch 2.13.0+cu130. Cells give the share of output elements that differ: vs diffusers / vs this kernel, where 0 means bitwise identical.

Implementation	T = 1	T = 4	T = 64	T = 2048
rl-kernel	92.1% / —	94.5% / —	97.8% / —	97.8% / —
vLLM settings	0 / 92.1%	93.9% / 90.6%	0 / 97.8%	0 / 97.8%
SGLang BI (TF32)	100.0% / 100.0%	100.0% / 100.0%	100.0% / 100.0%	100.0% / 100.0%
SGLang BI, ieee	97.7% / 98.4%	97.7% / 97.8%	0 / 97.8%	0 / 97.8%
Megatron te_native	0 / 92.1%	93.9% / 90.6%	0 / 97.8%	0 / 97.8%
Megatron triton (TF32)	100.0% / 100.0%	100.0% / 100.0%	100.0% / 100.0%	100.0% / 100.0%
Megatron triton, ieee	97.7% / 98.4%	97.7% / 97.8%	0 / 97.8%	0 / 97.8%

Results (B200, pinned time_embedder weights)

	RL-Kernel CUDA	diffusers (cuBLAS)
latency T = 1 / 2 / 4	36 / 40 / 45 µs	41 / 85 / 89 µs
max abs error vs FP64, median of 200 draws	1.1e-6	5.4e-7
row bitwise-invariant (alone vs batch of 9)	yes	no guarantee
gradients vs FP64 autograd	≤ 1.2e-5	n/a

Both outputs are about 100× inside the contract (atol 1e-4). Neither is more accurate in general;
the gains here are determinism and 2× speed for T ≥ 2. The data is in
reports/experiments/h3-timestep-mlp-b200/report.json, written from a clean tree at 418998c.

Status

• Seeded the evidence report's timing inputs (fb1bd8aa). _mlp_perf in h3_report.py drew its timestep features from the process's default CUDA generator, so the inputs depended on how many draws ran first; they are now seeded per T. No reported accuracy field depends on them, so the committed report is unchanged.

• Added: existing-implementation comparison, committed (tools/validation/models/h3_prior_art.py; report and figure for this op in reports/experiments/h3-prior-art-b200). Since 0fd6210 the branch gained only that runner, its evidence and the merges carrying them through the stack (no change outside docs/ and those scripts). See Prior art.

• Open: reuse decision. SGLang's and Megatron's Triton batch-invariant modes make this MLP batch-invariant (an earlier revision of this body said none existed). This kernel is faster and more accurate at H3's T = 1–4 and slower from T = 256. The question for the maintainers is under Prior art.

History

• 2026-10-26: one timing harness for the stack (reply to the bot finding on the unseeded timing order). The shuffled order added on 10-25 (cb9828f8) was replaced by the rotating harness the later PRs use (9a748eb2 and 31f342d7): each iteration times every callable once, the first callable changes from iteration to iteration, and the raw CUDA-event samples (timing_samples_us) and the executed order (timing_order) are stored next to the medians. A stub-clock test checks the bookkeeping and a real-GPU matmul test runs it. Measured on one idle B200 (9 rounds, 6 sizes): timing candidates in blocks, in either block order, differs by less than 0.6%; timing a callable in a block of its own reports 8-23% lower latencies for short kernels than interleaved timing; ratios and ranking do not change. The published latency tables predate this harness and stay provisional until regenerated with it.
• 2026-10-25/26: weight source recorded. The timestep MLP evidence now states which weights it used (a74b1a5a, 9beb1407, 31f342d7): the report carries h3_weights_source() additively, check_weight_source in h3_evidence.py refuses random weights unless --allow-random-weights is passed, and the figure title names the source.
• 2026-10-26: the stack is one ancestor chain. [WS1][CUDA][MiniMax-H3] timestep_sinusoid_h3: FP32 timestep features + shared H3 harness (RFC #420 stack 1/10) #483 → [WS1][CUDA][MiniMax-H3] timestep_mlp_fp32: deterministic FP32 timestep MLP (RFC #420 stack 2/10) #484 → … → [WS2][CUDA][MiniMax-H3] sp_norm_adaln: sequence-parallel norm/AdaLN/gated residual, byte-equal to WS1 (RFC #420 stack 9/10) #494 are merged forward in order (merge commits only, no force-push), so each branch contains its parent's head and merging the PRs in order does not conflict. All commits are signed off; GitHub's DCO check reports "could not be evaluated" on PRs above 250 commits ([WS2][CUDA][MiniMax-H3] tp_adaln_3mod: column-parallel AdaLN projection, byte-equal to WS1 (RFC #420 stack 8/10) #493, [WS2][CUDA][MiniMax-H3] sp_norm_adaln: sequence-parallel norm/AdaLN/gated residual, byte-equal to WS1 (RFC #420 stack 9/10) #494), which is an app limit, not a missing sign-off.
• 2026-10-23: history rewritten. Measurement outputs (JSON, figures, audit files) were removed from every branch and live on pr_assets (see the evidence note at the top), and all commits got a Signed-off-by trailer. Commit hashes in this body, including the clean-tree commit of the measurement, are the rewritten ones; the ZIPs and JSON files on pr_assets still carry the pre-rewrite hashes.
• 2026-10-13: fast-math guard (from the #483 review). KERNEL_ALIGN_USE_FAST_MATH=1 adds --use_fast_math to the whole _C build, which approximates expf/sinf/cosf/rsqrtf/division and flushes denormals. Before the fix a fast-math build of the top of the stack failed 33 H3 tests (the timestep_sinusoid_h3 and h3_rmsnorm bitwise tests and the chain/block tests built on them). nvcc 13 defines no fast-math macro, so the guard is in the build: every csrc/cuda/h3 source is listed in H3_BITWISE_SOURCES and left out of fast-math builds, the bindings are gated on KERNEL_ALIGN_WITH_H3_KERNELS, dispatch falls back to the PyTorch references, and tests that assert CUDA dispatch skip through require_h3_kernels. On this branch: merge e04594bf (adds det_linear.cu to the list). Results for both builds are under Tests.
• 2026-10-10: repository refactor. Merged upstream test-h3@16b81175874e (notice): H3 CUDA code moved to rl_engine/backends/cuda/model_specific/minimax_h3, references to rl_engine/reference/minimax_h3, the harness to rl_engine/validation/models, with registration, build, tests, tools, docs and tools/migration/layout.json updated. Native arithmetic is unchanged; pinned evidence keeps its original commit metadata.
• Earlier test runs, superseded by Tests below: after the refactor merge (2× B200): 92 passed, 0 skipped; with the fast-math guard (2× B200, passed / skipped / failed): default 105 / 8 / 0, fast-math 57 / 56 / 0.

Pre-refactor validation (historical, before 2026-10-10)

python -m pytest tests/models/minimax_h3/test_h3_conditioning_e2e.py -v     # end to end: sinusoid -> MLP
python -m pytest tests/models/minimax_h3/test_h3_timestep_mlp.py -v          # operator
python tools/validation/operators/check_operator.py --op timestep_mlp_fp32 --candidate cuda --device cuda --dtype fp32 --batch 3 --check-grad
python tools/validation/models/h3_evidence.py --op timestep_mlp_fp32 --out report.json && python tools/validation/models/plot_h3_evidence.py report.json

Check	Result
tests/models/minimax_h3 + dispatch + gtest-GPU	80 passed; the 1 failure is the npu dispatch test that already fails on test-h3
gtest fp32 --check-grad (H3 sizes)	passed: forward 4.2e-7, gradients ≤ 2.4e-6

The repository's CI workflows (ci.yml, gpu-ci.yml) only run on PRs to main or test, so on test-h3 only the DCO and CodeRabbit checks run. The results above come from local runs on one B200.

Tests

Measured at commit fb1bd8aa, an earlier head of this PR (later commits are listed under History and these runs were not repeated for the current head), 2× B200, pinned MiniMax-H3@42ed227 weights; each build compiled from a clean checkout of that commit:

python tools/weights/prepare_h3_weights.py --out <dir> && export RL_KERNEL_H3_WEIGHTS=<dir>
python setup.py build_ext --inplace                                  # default build
python -m pytest tests/models/minimax_h3 tests/build tests/runtime/test_dispatch.py -q
KERNEL_ALIGN_USE_FAST_MATH=1 python setup.py build_ext --inplace     # fast-math build, same pytest

Build	H3 kernels in _C	passed / skipped / failed
default	yes	111 / 2 / 0
KERNEL_ALIGN_USE_FAST_MATH=1	no (PyTorch reference fallback)	57 / 56 / 0

Default-build skips (environment only): 1 × could not import 'sglang.kernels.ops.diffusion.modulate.timestep_embedding_jit'; 1 × extension enforcement is CI-only (orchestrator sets RL_KERNEL_REQUIRE_EXT=1).

Fast-math regression tests: tests/build/test_build_platform_collectives.py::test_cuda_build_compiles_h3_kernels_without_fast_math, ::test_fast_math_build_excludes_bitwise_h3_kernels, tests/runtime/test_dispatch.py::test_h3_timestep_falls_back_when_fast_math_build_omits_kernel, ::test_h3_ops_prefer_cuda_and_fall_back_to_pytorch_reference.

On this PR the GitHub checks are DCO and CodeRabbit only (the CPU lint/unit/docs workflow for test-h3 arrives with #586), so the GPU results above are the test evidence.

Scope / Known limitations

CUDA only. The ROCm column stays open. ROCm dispatches the PyTorch reference, and a HIP port
of the warp-level code needs AMD hardware validation.

Summary by CodeRabbit

• New Features
  • Added MiniMax-H3 timestep sinusoid and FP32 timestep MLP operations, with PyTorch reference implementations and CUDA support where available.
  • Added deterministic linear operations for the timestep MLP, including forward and gradient calculations.
  • Added utilities to prepare and validate MiniMax-H3 conditioning weights.
• Documentation
  • Added operator guides describing input requirements, backend support, numerical behavior, and limitations.
• Tools
  • Added benchmarking, validation, and visualization tools for reviewing operator performance, accuracy, and consistency.

Results (H100 / Hopper)

Measured on 4 x NVIDIA H100 80GB (sm90), driver 580, CUDA 13.0.88, torch 2.13.0+cu130, pinned MiniMax-H3@42ed227, clean tree at 3b74ce35. Evidence files live on the pr_assets branch under pr484/reports/experiments/*-h100/.

Tests (pytest tests/models/minimax_h3 tests/build tests/runtime/test_dispatch.py)

• default build: 111 passed, 2 skipped in 6.65s
• KERNEL_ALIGN_USE_FAST_MATH=1 build: 57 passed, 56 skipped in 8.02s (the fast-math build omits the H3 CUDA sources to keep bitwise parity, so H3 CUDA tests skip there)

Bitwise vs diffusers: every case and tensor matches the B200 result (same equal / not-equal outcome on the shared diffusers and rl_kernel entries).

Backward (H100): gradients of the op on identical inputs and upstream gradients, each run twice, sizes 1, 4, 64, 2048. The kernel gradient is bitwise repeatable for every gradient at every size. Errors are max|err| / max|ref| against an FP64 autograd of the reference formula at size 2048; "det diffusers" is the same diffusers replay under torch.use_deterministic_algorithms(True).

gradient	kernel repeatable	native diffusers repeatable	kernel error	native diffusers error	det diffusers error	kernel == det diffusers bitwise
x	yes	yes	3.8e-07	1.1e-06	1.1e-06	no
w1	yes	yes	1.9e-06	1.1e-06	1.1e-06	no
b1	yes	yes	1.8e-06	9.8e-07	9.8e-07	no
w2	yes	yes	2.1e-06	1.4e-06	1.4e-06	no
b2	yes	yes	1.7e-06	1.1e-07	1.1e-07	no

Data and runner: h3-backward-h100/ on pr_assets (commit 37a9e6ad).

Repeat check with 30 replays per size (report): native diffusers, deterministic diffusers and the kernel all give 1 distinct bitwise result for every gradient and size (no gather, no atomics in this op).

This is an FP32 MLP: kernel and diffusers are at the same rounding level (kernel 0.3x to 16x of diffusers on individual tensors, all below 2.1e-06), and the kernel is not bitwise equal to diffusers because the reduction order differs.

Figures

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Files selected for processing: 5

• rl_engine/validation/models/h3_report.py
• tests/models/minimax_h3/test_h3_report.py
• tests/models/minimax_h3/test_h3_report_timing.py
• tests/models/minimax_h3/test_h3_weight_source.py
• tools/validation/models/h3_evidence.py

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Walkthrough

This PR adds MiniMax-H3 sinusoidal timestep and FP32 timestep MLP operators. It provides PyTorch reference and CUDA implementations, runtime dispatch, deterministic linear kernels, validation and evidence tools, weight preparation utilities, and operator documentation.

Changes: MiniMax-H3 Timestep Conditioning

Layer / File(s)	Summary
Reference operators and numerical contracts rl_engine/reference/minimax_h3/*	Adds H3 dimensions, validation, sinusoid and MLP reference operators, FP64 comparison paths, and fixed-order FP32 reduction helpers.
CUDA kernels and extension bindings csrc/cuda/h3/*, csrc/bindings/ops.cpp, build_tools/extensions.py, rl_engine/_C.pyi	Adds CUDA sinusoid and deterministic linear forward/backward kernels, validates supported tensor configurations, exposes the operators through bindings, and includes the kernels only when fast math is disabled.
CUDA operators and backend dispatch rl_engine/backends/cuda/model_specific/minimax_h3/*, rl_engine/runtime/registry.py	Adds CUDA wrappers and autograd implementations. CUDA dispatch tries the H3 CUDA operators before the PyTorch implementations; ROCm, MUSA, and CPU dispatch use the PyTorch implementations.
Operator inputs and chained evaluation rl_engine/validation/operators/*, rl_engine/validation/models/h3_cases.py, rl_engine/validation/models/h3_chain.py, rl_engine/validation/models/h3_provider.py, rl_engine/validation/models/h3_report.py	Adds operator input builders and specifications, seeded H3 cases, provider comparisons, chained candidate/provider/golden evaluation, and accuracy and performance measurements.
Pinned weights, evaluation, and evidence rl_engine/validation/models/h3_manifest.json, rl_engine/validation/models/h3_weights.py, tools/weights/prepare_h3_weights.py, tools/validation/models/*, benchmarks/models/benchmark_h3_conditioning.py, tools/migration/*	Adds manifest-checked weight preparation and loading, CUDA validation and replay tools, report plotting, a benchmark, and migration path mappings.
Operator validation and documentation tests/build/test_build_platform_collectives.py, tests/models/minimax_h3/*, tests/runtime/test_dispatch.py, tests/validation/operators/test_ws1_gtest_gpu.py, docs/operators/*, docs/.nav.yml, docs/operators/README.md	Adds tests for build configuration, dispatch, input validation, numerical behavior, gradients, determinism, and end-to-end execution. Adds H3 operator documentation and navigation links.

Priority: Normal

Estimated code review effort: 5 (Critical) | ~120 minutes

Change: Feature

Sequence Diagram(s)

sequenceDiagram
  participant Caller
  participant KernelRegistry
  participant H3TimestepMLPCudaOp
  participant det_linear
  participant CUDAExtension
  Caller->>KernelRegistry: select timestep_mlp_fp32 backend
  KernelRegistry->>H3TimestepMLPCudaOp: select CUDA implementation
  H3TimestepMLPCudaOp->>det_linear: run two linear layers and SiLU
  det_linear->>CUDAExtension: call deterministic linear operators
  CUDAExtension-->>det_linear: return outputs and gradients
  det_linear-->>H3TimestepMLPCudaOp: return MLP result
  H3TimestepMLPCudaOp-->>Caller: return result

Loading

Possibly related issues

• RL-Align/RL-Kernel#420 — This PR implements the H3 CUDA FP32 timestep MLP target described in the roadmap; it does not cover the full roadmap.

Possibly related PRs

• RL-Align/RL-Kernel#483 — The PRs share the H3 sinusoid kernel, runtime registration, and validation harness; this PR also adds the MLP that consumes sinusoid features.

Merge Risk: Low · previous review 9beb1

Without configured pinned weights, the evidence command wastes a full GPU measurement run before rejecting the report. This is a bounded workflow cost rather than a blocker to merging.

Security Architecture Review

Security architecture risk: 🔵 Low · up to 813cd

The new GPU operators retain input validation at the native boundary and keep execution tied to the caller’s device and stream. No introduced security concern was established in the inspected paths. Downstream deployment exposure and runtime failure behavior remain unverified.

Retained concerns
No architecture-level concerns identified.

Security review details

Security Blast Radius

• inferred — The evidenced exposure is callable native execution within the importing process and its CUDA context. A caller selects tensors and dimensions, potentially consuming GPU compute and memory. The inspected callers do not establish a remote, cross-tenant or privileged service boundary; downstream exposure remains unknown.

Trust Boundaries and Controls

• observed — Native deterministic-linear entrypoints independently reject incompatible devices, shapes and dtypes. Forward also enforces contiguity, base-pointer alignment and vector-width-compatible K. These checks remain effective for direct extension calls that bypass Python wrapper normalization.

Resilience and Maintainability Implications

• inferred — Per-call allocations, device guards and same-stream launches support isolation between calls and ordered consumption of temporary gradients. Launch checks occur before returning outputs, and the partial-gradient launch is checked before its consumer is enqueued. These controls do not establish recovery from asynchronous CUDA execution faults, which was not exercised.

Hardening Proposals

• proposed — If extracted weights are shared across users or used as authoritative evidence, consider content verification at consumption and atomic publication through a unique temporary file. This would strengthen integrity across local modification, interrupted writes and concurrent preparation; it is not an established PR security finding.

Pre-merge checks: 4 · 1

Failed checks: 1 warning

Check name	Status	Explanation	Resolution
Docstring Coverage		Docstring coverage is 11.74% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 460 functions across 74 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

Passed checks: 4 passed

Check name	Status	Explanation
Title check		The title clearly identifies the main change: a deterministic FP32 MiniMax-H3 timestep MLP implemented for CUDA. The stack and RFC identifiers add context without making the title misleading.
Linked Issues check		Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check		Check skipped because no linked issues were found for this pull request.
Description Check		Check skipped - CodeRabbit’s high-level summary is enabled.

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Inline comments:
Review comments at @csrc/cuda/h3/det_linear.cu:
- Around line 389-393: Add device-equality checks in the backward wrappers that
validate grad against weight or x before launching kernels, and require optional
bias in the forward path to share weight.device(). Keep the existing shape,
dtype, and contiguity checks intact.

Review comments at @docs/operators/h3-timestep-mlp.md:
- Around line 98-104: Update the performance table in the H3 timestep MLP
documentation to match the committed report.json values for CUDA op and provider
timings, or identify the run that produced the current values so readers can
trace them to evidence. Keep the kernels-only measurements unchanged unless the
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Reviewing files that changed from the base of the PR and between 32b765e and 6383a08.

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• docs/usage/evidence/h3-timestep-mlp-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/h3-timestep-sinusoid-b200/figure.png is excluded by !**/*.png

📒 Files selected for processing (39)

• benchmarks/benchmark_h3_conditioning.py
• csrc/cuda/h3/det_linear.cu
• csrc/cuda/h3/timestep_sinusoid.cu
• csrc/ops.cpp
• docs/.nav.yml
• docs/operators/README.md
• docs/operators/h3-timestep-mlp.md
• docs/operators/h3-timestep-sinusoid.md
• docs/usage/evidence/h3-timestep-mlp-b200/report.json
• docs/usage/evidence/h3-timestep-sinusoid-b200/report.json
• rl_engine/_C.pyi
• rl_engine/kernels/gtest/operator_inputs.py
• rl_engine/kernels/gtest/operator_specs.py
• rl_engine/kernels/ops/cuda/h3/__init__.py
• rl_engine/kernels/ops/cuda/h3/det_linear.py
• rl_engine/kernels/ops/cuda/h3/timestep_mlp.py
• rl_engine/kernels/ops/cuda/h3/timestep_sinusoid.py
• rl_engine/kernels/ops/pytorch/h3/__init__.py
• rl_engine/kernels/ops/pytorch/h3/fixed_order.py
• rl_engine/kernels/ops/pytorch/h3/timestep_mlp.py
• rl_engine/kernels/ops/pytorch/h3/timestep_sinusoid.py
• rl_engine/kernels/registry.py
• rl_engine/testing/h3_cases.py
• rl_engine/testing/h3_chain.py
• rl_engine/testing/h3_manifest.json
• rl_engine/testing/h3_provider.py
• rl_engine/testing/h3_report.py
• rl_engine/testing/h3_weights.py
• rl_engine/tests/test_dispatch.py
• scripts/h3_chain_replay.py
• scripts/h3_evidence.py
• scripts/plot_h3_evidence.py
• scripts/prepare_h3_weights.py
• setup.py
• tests/h3/conftest.py
• tests/h3/test_h3_conditioning_e2e.py
• tests/h3/test_h3_timestep_mlp.py
• tests/h3/test_h3_timestep_sinusoid.py
• tests/test_ws1_gtest_gpu.py

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[github-actions]

The H3 bitwise sources are only coupled to --use_fast_math, but this branch already treats KERNEL_ALIGN_FORCE_SM90=1 as a build that defines KERNEL_ALIGN_WITH_SM90 (varying compilation separately for the SM90 DSO). nvcc has no macro for fast math, so the .cu files themselves cannot detect it — but they can detect KERNEL_ALIGN_WITH_SM90, and any future/NVCC_PREPEND_FLAGS-style flag path (e.g. -use_fast_math via NVCC_APPEND_FLAGS, which is not rejected in the non-strict profile) silently produces H3 kernels with relaxed expf/cosf/sinf and still registers the bindings, breaking the bitwise contract with no runtime warning. At minimum, the omission of these sources should be keyed off a single "precision-safe build" predicate that also covers other arithmetic-changing flags, and/or the .cu files should #error when a incompatible define is set so the build fails instead of shipping non-bitwise kernels.

[fusheng-ji]

Fixed in c0b4cd8 (#483, where the build file lives; this PR contains it). build_tools/extensions.py now computes one h3_enabled predicate that gates both the csrc/cuda/h3 sources and -DKERNEL_ALIGN_WITH_H3_KERNELS, so the bindings cannot outlive the kernels. NVCC_PREPEND_FLAGS, NVCC_APPEND_FLAGS and TORCH_NVCC_FLAGS carrying --use_fast_math, --ftz=true or --prec-div/--prec-sqrt=false leave the H3 kernels out with a warning, like KERNEL_ALIGN_USE_FAST_MATH=1, and dispatch falls back to the PyTorch reference. Tests: test_relaxed_math_nvcc_flags_from_the_environment_exclude_bitwise_h3_kernels (three variables) and test_unrelated_nvcc_flags_keep_the_h3_kernels.

[github-actions]

The N-tail guard is asymmetric. When n0 + c >= n_out the load is skipped, leaving raw[u][c] uninitialized, but the consume loop below only checks k0 >= k_in and still calls WV::unpack(raw[u][c], wv) and FMA's those indeterminate registers into acc[c][r]. For a warp whose column block straddles n_out (i.e. n_out % kCols != 0, which happens for any odd N with H3_FWD_F32_COLS=2 or N not a multiple of 4 in the bf16 config) this reads uninitialized registers — undefined behaviour that can raise FP invalid flags/NaNs, and the resulting acc[c][r] is then broadcast by warp_butterfly_sum across all lanes. Apply the same n0 + c < n_out guard in the consume loop (e.g. skip the column there), or zero-initialize raw[u][c].

[fusheng-ji]

Fixed in 0f66d75: the consuming loop is guarded with n0 + c < n_out like the load. Test: test_h3_det_linear_odd_width.py (N in {1, 2, 3, 5, 7, 9, 33, 65}, FP32 and BF16; golden and tail-independence), passed on a fresh B200 build.

[github-actions]

The forward loop requires k_in % kVec == 0, but each lane loads 16-byte vector chunks starting at lane*kVec and then strides by kStride; when k_in % kStride != 0 a lane's last chunk starts at k0 < k_in but extends past k_in, so WV::load_stream reads a full 16-byte vector beyond the end of the weight row. For example mismatched K values with bf16 (kVec=8, kStride=256) such as K=264: lane 33... let's be concrete — lane l whose chunk starts at l*8 with l*8 < 264 <= l*8+8 produces an out-of-bounds 16-byte read that can cross into the next tensor or past the allocation. The same over-read happens in XV::load(x + (t0 + r) * k_in + k0, xv) for the last row. Guard by requiring k_in % kStride == 0 (or masking the tail) before launching, so tail chunks are either fully in range or rejected explicitly.

[fusheng-ji]

Not changed. The host requires K % vec == 0 (vec = 16 / sizeof(T): 8 for BF16, 4 for FP32), and every vector or MMA load starts at a multiple of vec below K, so k < K already implies k + vec <= K; no load straddles the row end and every row start stays 16-byte aligned. Checked rather than argued: forward, input-gradient and weight-gradient kernels with BF16 K in {8, 24, 40, 72, 264, 520, 1032} and FP32 K in {4, 12, 20, 36, 132, 1044}, N in {1, 3, 17, 33}, rows in {1, 3, 5} ran under compute-sanitizer --tool memcheck with 0 errors and 0 mismatches against an FP64 golden. 0e911be adds the K sweep to test_h3_det_linear_odd_width.py.

[Flink-ddd]

Please guard this loop with n0 + c < n_out as well. For odd FP32 output widths, it reads raw[u][c] without initializing it. Please add an odd-width test to cover this case.

[fusheng-ji]

Fixed in 0f66d75. The loop that unpacks raw[u][c] and feeds the FMAs is now guarded with n0 + c < n_out, like the load above it, so the last column tile of an N that is not a multiple of kCols (any odd N for FP32, kCols = 2; N % 4 for BF16) no longer reads the uninitialized registers. The columns past n_out were never stored, but the read itself was undefined behaviour. This is the only place in det_linear.cu that consumes raw; the other kernels index their columns with n < n_out already.

Test: tests/models/minimax_h3/test_h3_det_linear_odd_width.py, N in {1, 2, 3, 5, 7, 9, 33, 65} for FP32 and BF16, rows 1/3/5. Forward is compared with an FP64 golden and bitwise with the leading columns of the same product with zero columns padded on; the input, weight and bias gradients get the same two checks. It passed on a B200 with a fresh build, and again on the branches above this one. A test cannot observe the uninitialized read itself, so it pins that odd widths give the golden result and do not depend on the tail.

The same guard closes the github-actions findings at det_linear.cu:139 on this PR and :155 on #493 (same loop). I did not change the :138 finding about a K over-read: the host already requires K % vec == 0, so no lane’s last 16-byte chunk starts inside the row and ends outside it.

[github-actions]

Epilogue lane guard lane == c * kRows + r silently drops stores whenever kCols * kRows > 32: lane is threadIdx.x % 32 so the maximum reachable index is 31. pick_forward_config selects H3_FWD_BF16_COLS = 4 with row_tile = 4 for any bf16 input with more than 2 rows, giving index 15 today, but the values are build-tunable #defines and the fallthrough TORCH_CHECK(false, "unsupported ...") only covers cols/ahead, not the product bound. A config with kCols * kRows > 32 compiles fine, launches fine, and leaves parts of out/pre_act as uninitialized torch::empty garbage (bitwise contract silently violated). Add a static_assert(kCols * kRows <= kWarp, ...) in the kernel (or in pick_forward_config) so an out-of-range config is a build failure rather than silent data corruption.

[fusheng-ji]

Fixed in 0e911be: static_assert(kCols * kRows <= kWarp) in the forward kernel, so a tuned config above a warp fails the build instead of dropping stores.

[github-actions]

The custom Function saves hidden (the FP32 SiLU output) in ctx.save_for_backward, but that tensor is a non-leaf intermediate produced by _C.h3_det_linear_forward. save_for_backward only accepts inputs/outputs of the Function or tensors with no grad history; a tensor that is a graph output of another autograd node raises RuntimeError: Trying to save a Tensor that requires grad on torch>=2.x when grad mode is enabled on the outer graph. Since forward does not wrap the call in torch.no_grad() and the docstring says the MLP feeds the training path, this fails as soon as the op is used with grad enabled. Save hidden.detach() (and pre.detach(), x.detach()) or run the inner _C calls under torch.no_grad() so the intermediates carry no grad history.

[fusheng-ji]

Not an issue. torch.autograd.Function.forward runs under no_grad, so hidden/pre have no grad history and save_for_backward accepts them. The op is exercised with grad enabled by the backward tests in test_h3_timestep_mlp.py.

[github-actions]

Use-after-free on the async stream: timestep.contiguous() returns a new tensor that is only referenced by the local t. When the input is non-contiguous (e.g. a strided slice of a larger timestep buffer, which the Python op passes through since forward() only calls .detach().float(), not .contiguous()), the kernel reads from t.data_ptr<float>() asynchronously while t is destroyed at return, freeing the buffer before the kernel executes. Trigger: _C.h3_timestep_sinusoid_forward(ts[::2], ...) (or any strided view) — the config also enables CUDA caching-allocator reuse, so the memory can be re-allocated and overwritten by an unrelated op. Keep the temporary alive through the launch (e.g. at::cuda::CUDACachingAllocator::recordStream or hold t until after C10_CUDA_KERNEL_LAUNCH_CHECK() / return it in a tuple that keeps the storage referenced by the returned output's lifetime).

[fusheng-ji]

Not changed. t is destroyed when the function returns, but the kernel is launched on the current stream and the caching allocator only hands the freed block to later allocations on that same stream, which run after the kernel. A different-stream reuse would need the caller to move the output across streams, which this entry point does not do.

[github-actions]

torch::wrap_pybind_function is inconsistently applied: the three h3_det_linear_* ops are registered with the raw & function pointer. torch::wrap_pybind_function is what releases the GIL and re-acquires the current CUDA device around the call, so these ops run with the GIL held and (via pybind's implicit torch::Tensor caster) do not do the device-guard bookkeeping of the wrapped path. Please wrap them too, matching h3_timestep_sinusoid_forward.

Suggestion:

Suggested change

	m.def("h3_det_linear_forward", &h3_det_linear_forward,
	m.def("h3_det_linear_forward", torch::wrap_pybind_function(h3_det_linear_forward),

[fusheng-ji]

Not changed. torch::wrap_pybind_function does not release the GIL and does not touch the CUDA device: in torch 2.13 (torch/csrc/Exceptions.h) it instantiates wrap_pybind_function_impl_ with release_gil = false; the GIL-releasing variant is wrap_pybind_function_no_gil. What the wrapper adds is PyTorch's exception and warning translation. The device is handled inside the entry points: h3_det_linear_forward, h3_det_linear_backward_input and h3_det_linear_backward_weight each take a c10::cuda::CUDAGuard on their tensors' device before the first allocation or launch and read the stream after it. The sinusoid op keeps its wrapper for its own reason: it is the one H3 op that raises a typed error (TORCH_CHECK_VALUE, so the range check reaches Python as ValueError); the det_linear checks are plain TORCH_CHECKs that reach Python as RuntimeError either way (the validation tests assert those messages), and every other native op in ops.cpp is registered with the raw pointer. Pinned in 2ee5abc: test_ops_run_on_the_device_of_their_tensors_not_the_current_one calls forward and both backwards with the tensors on cuda:1 while cuda:0 is current, for FP32 and BF16, and compares the bytes with the same calls on cuda:0.

[github-actions]

h3_det_linear_backward_input / h3_det_linear_backward_weight are likewise registered with the raw function pointer, so these (potentially long, allocating) backward kernels run while holding the GIL and without torch::wrap_pybind_function's device handling. Wrap both for consistency with the other native ops.

Suggestion:

Suggested change

	m.def("h3_det_linear_backward_input", &h3_det_linear_backward_input,
	"Deterministic grad @ weight with fixed 64-row N chunks folded in order",
	py::arg("grad"), py::arg("weight"), py::arg("out_dtype"));
	m.def("h3_det_linear_backward_weight", &h3_det_linear_backward_weight,
	m.def("h3_det_linear_backward_input", torch::wrap_pybind_function(h3_det_linear_backward_input),
	"Deterministic grad @ weight with fixed 64-row N chunks folded in order",
	py::arg("grad"), py::arg("weight"), py::arg("out_dtype"));
	m.def("h3_det_linear_backward_weight", torch::wrap_pybind_function(h3_det_linear_backward_weight),

[fusheng-ji]

Not changed. torch::wrap_pybind_function does not release the GIL and does not touch the CUDA device: in torch 2.13 (torch/csrc/Exceptions.h) it instantiates wrap_pybind_function_impl_ with release_gil = false; the GIL-releasing variant is wrap_pybind_function_no_gil. What the wrapper adds is PyTorch's exception and warning translation. The device is handled inside the entry points: h3_det_linear_forward, h3_det_linear_backward_input and h3_det_linear_backward_weight each take a c10::cuda::CUDAGuard on their tensors' device before the first allocation or launch and read the stream after it. The sinusoid op keeps its wrapper for its own reason: it is the one H3 op that raises a typed error (TORCH_CHECK_VALUE, so the range check reaches Python as ValueError); the det_linear checks are plain TORCH_CHECKs that reach Python as RuntimeError either way (the validation tests assert those messages), and every other native op in ops.cpp is registered with the raw pointer. Pinned in 2ee5abc: test_ops_run_on_the_device_of_their_tensors_not_the_current_one calls forward and both backwards with the tensors on cuda:1 while cuda:0 is current, for FP32 and BF16, and compares the bytes with the same calls on cuda:0.

[github-actions]

std::min is used here but neither <algorithm> nor a using namespace is in scope (<cstdint> and <cmath> are the only includes added). On GCC/libstdc++ this usually compiles only by transitive inclusion, and it will fail on toolchains where <torch/extension.h> does not pull in <algorithm> first. Use std::min<int64_t> with an explicit #include <algorithm> (or, simpler, a plain ternary) so the file is self-contained.

Suggestion:

Suggested change

	const int64_t blocks = std::min<int64_t>((total + threads - 1) / threads, 65535);
	const int64_t blocks = std::min<int64_t>((total + threads - 1) / threads, 65535); // requires <algorithm>

[fusheng-ji]

Fixed in ac225c7 (#483, where timestep_sinusoid.cu lives; this PR contains it): #include <algorithm> is there now. std::min<int64_t> was already explicit.

[github-actions]

torch::empty({num_timesteps, num_channels}, t.options()) is exactly num_timesteps * num_channels elements, but only one element per (row, k) with k < half is written for the sin half? No — both halves are written, so the buffer is fully covered. The real bug is that blocks can be 0 when total < threads? min((total+255)/256, 65535) is at least 1 for total > 0, which is guaranteed by the num_timesteps > 0 / num_channels > 0 checks. No further issue.

[fusheng-ji]

Not changed. The finding checks itself and finds no defect: both halves are written (the grid-stride loop covers total = T * half, cos goes to [row, k] and sin to [row, half + k]), and blocks >= 1 because total > 0 follows from the num_timesteps > 0 and num_channels > 0 checks.

[github-actions]

The guard only inspects NVCC_PREPEND_FLAGS / NVCC_APPEND_FLAGS / TORCH_NVCC_FLAGS, but relaxed FP32 math also arrives through paths that are never checked here, notably CFLAGS/CXXFLAGS/CPPFLAGS inherited by nvcc and extra flags coming from setup.cfg/pyproject config (also NVCC_PREPEND_FLAGS inside an --options-file referenced by CFLAGS). In those builds h3_enabled stays True: the H3 .cu sources are compiled and KERNEL_ALIGN_WITH_H3_KERNELS is defined, yet the kernels are built with relaxed math/FTZ, silently violating the bitwise parity contract this change promises. Consider failing closed (or at least warning) when CFLAGS/CXXFLAGS/CPPFLAGS mention any of the relaxed-math spellings (use_fast_math, ftz, prec-div, prec-sqrt), or document/enforce that those variables are unsupported for H3 builds.

[fusheng-ji]

Not changed. nvcc does not read CFLAGS, CXXFLAGS or CPPFLAGS: with all three set to --use_fast_math --ftz=true --prec-div=false, nvcc --dryrun on a division kernel prints none of those options, same as with no variables set (checked with nvcc 13.0). The channels it does read are NVCC_PREPEND_FLAGS, NVCC_APPEND_FLAGS and, through the torch build, TORCH_NVCC_FLAGS; _relaxed_math_reason() covers those, including --options-file/-optf files named in them. -Xcompiler, -Xptxas and -Xcudafe pass options to the host compiler, ptxas and the front end and do not change -ftz or -prec-div, which are cicc options. The ; separator of TORCH_NVCC_FLAGS is handled by the lexer (; is a separator, quoted words stay whole) and the tests added in 562d3fa3 cover it.

[Flink-ddd]

LGTM. The fixes and regression tests address the review concerns. also cc @maxiaosong1124 PTAL

[maxiaosong1124]

LGTM!

[github-actions]

Only k_in % vec == 0 (and check_matrix's 16-byte base alignment) is enforced, but the forward kernel also does 16-byte vector loads of x starting at x + (t0 + r) * k_in + k0. Row starts are therefore only 16-byte aligned if k_in * sizeof(T) is itself a multiple of 16. For bf16, vec = 8 admits k_in % 8 == 0 but not k_in % 16 == 0, and for float vec = 4 admits k_in % 4 == 0 but not k_in % 16 == 0; e.g. bf16 with k_in = 8 (or float with k_in = 4) makes every row after the first start at a non-16-byte boundary, so XV::load / WV::load_stream reads misaligned uint4 — undefined behaviour (misaligned access fault on some paths, silently degraded loads on others). The host check must require the row byte pitch to be a multiple of 16, not just vec elements.

Suggestion:

Suggested change

	const int64_t vec = 16 / x.element_size();
	TORCH_CHECK(k_in % vec == 0, "K=", k_in, " must be a multiple of ", vec,
	" for 16-byte vector loads");
	// Rows are loaded with 16-byte vector loads, so the byte pitch of a row must be a multiple of 16.
	TORCH_CHECK((k_in * x.element_size()) % 16 == 0, "K=", k_in, " * ", x.element_size(),
	" bytes per element is not a multiple of 16; row starts would be unaligned");