Platform/ARM/VExpressPkg: Code first ACPI boot support with GICv5#931
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LeviYeoReum wants to merge 5 commits intotianocore:masterfrom
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Platform/ARM/VExpressPkg: Code first ACPI boot support with GICv5#931LeviYeoReum wants to merge 5 commits intotianocore:masterfrom
LeviYeoReum wants to merge 5 commits intotianocore:masterfrom
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Generate SRAT table. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
This patch add support for GICv5 in FVP_RevC model. For this: - add IRS, ITSv5, IWB information. - add DSDT for GicV5. - update IORT information. - update Platform repository when GICv5 is supported. Signed-off-by: Sarah Walker <Sarah.Walker@arm.com>
Currently, platform coordinated LPI isn't supported with gic-v5. Therefore, disable it. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Update PCI interrupt value from SPI to IWB and _PRT table entry. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
add documents for GICv5 support with FVP_RevC model. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Could you label this pr with type:code-first? I coudln't edit the labels of this PR.. |
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This patch set adds support for booting with GICv5
on the FVP_RevC platform.
To achieve this, it generates GICv5-related information
in the ACPI tables based on the code-first definitions described in [1].
All GICv5 structures and ACPI table updates are planned to
be published as part of ACPI 6.7.
Booting with GICv5 has been tested using
the corresponding GICv5-related kernel patches [2] and
with tianocore/edk2#11998 [4].
You can download the latest FVP_RevC model with GICv5 in [3].
Link: tianocore/edk2#11148 [1]
Link: https://lore.kernel.org/all/20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org/ [2]
LInk: https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/Arm%20Architecture%20FVPs [3]
Resolve: tianocore/edk2#11148
Link: tianocore/edk2#11998 [4]
Co-developed-by: Sarah Walker Sarah.Walker@arm.com
Signed-off: Yeoreum Yun yeoreum.yun@arm.com