Platform/ARM/VExpressPkg: Code first ACPI boot support with GICv5#929
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LeviYeoReum wants to merge 4 commits intotianocore:masterfrom
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Platform/ARM/VExpressPkg: Code first ACPI boot support with GICv5#929LeviYeoReum wants to merge 4 commits intotianocore:masterfrom
LeviYeoReum wants to merge 4 commits intotianocore:masterfrom
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Generate SRAT table. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
This patch add support for GICv5 in FVP_RevC model. For this: - add IRS, ITSv5, IWB information. - add DSDT for GicV5. - update IORT information. - update Platform repository when GICv5 is supported. Signed-off-by: Sarah Walker <Sarah.Walker@arm.com>
Currently, platform coordinated LPI isn't supported with gic-v5. Therefore, disable it. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Update PCI interrupt value from SPI to IWB and _PRT table entry. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Move to #931 as Draft following guide: |
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This patch set adds support for booting with GICv5
on the FVP_RevC platform.
To achieve this, it generates GICv5-related information
in the ACPI tables based on the code-first definitions described in [1].
All GICv5 structures and ACPI table updates are planned to
be published as part of ACPI 6.7.
Booting with GICv5 has been tested using
the corresponding GICv5-related kernel patches [2].
[1] tianocore/edk2#11148
[2] https://lore.kernel.org/all/20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org/