Conversation
* Replace assembly macros in smp.h with C functions (smp_resume, barriers) * Add explicit _wait_for_ipi in bootrom using call smp_resume * Add per-hart stack sizing in crt0.S * Guard ZSL single-hart work behind hart_id == 0, call smp_resume * Add dual-core testbench config and PLIC target generation script * Add smp_hello test Co-authored-by: Enrico Zelioli <ezelioli@iis.ee.ethz.ch> Co-authored-by: Emanuele Parisi <emanuele.parisi@protonmail.com>
There was a problem hiding this comment.
This barrier implementation is unfortunately not correct. It was wrongly adapted (by me, sorry :')) from the CHERI Litmus tests simple barrier implementation (https://github.com/CTSRD-CHERI/CHERI-Litmus/blob/master/backend/riscv/arch.c). Simply adding a second barrier_target variable and repeating the count up/down + wait on it would suffice to avoid race conditions. This is not an efficient nor elegant implementation, but if intended for bare-metal simple tests it should be fine.
Another simple but slightly better implementation which removes the count up / down alternation requirement would be a sense-reversing centralized barrier (https://www.cs.rochester.edu/~scott/papers/1991_TOCS_synch.pdf). Again, I think that for the Cheshire use case of it would be fine to keep a fixed version of the current implementation.
|
|
||
| static volatile uint64_t _barrier_target = 0; | ||
|
|
||
| static void barrier_wait(volatile uint64_t *barrier, uint64_t incr, uint64_t reach) { |
There was a problem hiding this comment.
Another typo, the incr parameter should probably be int64_t
|
One conceptual point which might be worth discussing is whether the current approach of the bootrom of having all cores jumping to the next boot stage is what we want. I think is fine and I personally prefer this over parking secondary harts and exposing an API to resume them, but this could be an option worth considering. |
|
|
||
| #include "smp.h" | ||
|
|
||
| void smp_resume(void) { |
There was a problem hiding this comment.
This implicitly assumes that NONSMP_HART is 0, which is fine as long as the macro in smp.h is not changed. Maybe a comment making this explicit would be helpful, or a modified version which counts from 0 to num_harts - 1 and skips an iteration when i == core_id.
2 participants
This PR aims at enabling support for baremetal multi-core execution. It rebases #169 on the latest changes.