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PMAT-3477: Qwen3.5 (Gated DeltaNet hybrid) runs on CUDA — nine device kernels, Qwen35CudaModel, refusal sites lifted, apr run/chat/qa route to the GPU (#3090) - #3517
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…orm, gates, delta-rule recurrence, gated RMSNorm, sigmoid gate — each against a host port of the CPU reference (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…e split kernels for the Qwen3.5 attention layers (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…s and the DeltaNet layer forward on the GPU, every DeltaNet layer matching the CPU forward on the real 0.8B file (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
… forward — argmax matches the CPU at every position on the real 0.8B file (#3090) The three attention-side kernels are wired through the executor (split q|gate, partial NEOX rope with a HOST-computed theta_scale, head_dim-256 decode attention), the attention layers upload their tensors and own device K/V caches, and forward_single runs a whole token through both layer kinds, the output norm and the lm_head. Op-by-op against the CPU on the GPU's own inputs: every attention stage is inside 1e-3 relative. Skipping gdn_sigmoid_gate_into turns that test RED at 1.047e0, so the gate is load-bearing. End to end over six tokens the argmax is IDENTICAL at every position (13, 198, 11, 198, 0, 908) but the logit L-inf is 2.0e-2..6.7e-2, not the 1e-3 the test asks for. The new parity-floor test says why: on attn_q the GPU float GEMV is 9.96e-8 from an exact dequantized f64 dot while the CPU fused_matmul_into is 2.95e-3 from it, because it quantizes the ACTIVATION to Q8_K. The reference is the noisier side, so no correct GPU implementation can sit inside 1e-3 of it. Two tests are left RED rather than have their tolerances moved; what the bar should be is a decision, not a fix. Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…ate, parity, ptx-map, quant whitelist and the SSM predicate now agree with the hybrid forward (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…through the recurrence); parity restated to per-op exact ≤1e-3 plus e2e argmax equality with a measured cosine floor (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…ard judges the hybrid against its own CPU forward; no silent CPU fallback (#3090) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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§13.11 rung 1 — quorum shadow verdict Shadow mode: this records a verdict and merges nothing. A refusal |
… stream syncs, LM head on device, one logits download; floor test no longer re-pins (#3090 review) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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…lt from main with the nine GDN variants appended, speedup.rs leading blank restored; review quorum artifact for #3517 Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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… hosts — eight rungs with sha256, RED by construction on Qwen3.5 (paiml#3510) (paiml#3523) * evidence(ladder): 0.68.1 receipts re-measured at main a6f54e8 on both hosts — all eight rungs with sha256, RED by construction on the Qwen3.5 rungs (paiml#3510, ONT-4c1 witness) Both receipts produced by scripts/model_ladder.sh at a6f54e8 (the first main with paiml#3507's sha256 rows and paiml#3511's four dense rungs), apr 0.68.1 (a6f54e8), lambda RTX 4090 cc 8.9 and gx10 GB10 cc 12.1. Every rung present, sha_ok, and carries the measured sha256 — the witness ONT-4c1's ladder-measured shape needs on day one. Green: qwen2-1.5b, qwen3-1.7b (both hosts), qwen3-8b (gx10; lambda optional rung: golden Empty output, paiml#3486). Red by construction: qwen35-0.8b/2b fall back to CPU on main until paiml#3517 merges; qwen35-4b/9b/27b exit 101 at forward_qwen35.rs:132 (GQA inside GDN, nk != nv — paiml#3346 root cause). The T-2 judge is not a PR check; this changes no gate. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * audit: quorum artifact for PR paiml#3523 (3/3 PASS, PMAT-3524) Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> --------- Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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* release: 0.68.2 bump-version.sh 0.68.2 (every workspace, facades included; --check green) and the CHANGELOG [0.68.2] section, per docs/specifications/06x-release-schedule.md §4.2. After this merges, rel-0682-autopilot runs APR-RELEASE-001 §4 T-1..T-4 + close: deep (T-1, local), pre-publish dogfood, tag + release, clean-room.yml dispatched on the tag (T-3, run id recorded), assets by command, preflight, cascade (T-4, automated), install, host + installer receipts, close. Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * release: 0.68.2 CHANGELOG — Qwen3.5 on CUDA up to 27B (paiml#3517, paiml#3527) and every PR merged since v0.68.1 Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * evidence(ladder): 0.68.2 receipts measured from the bump tree on lambda (sm_89) and gx10 (sm_121) — every required rung green on both hosts; qwen3-8b optional red on lambda (paiml#3532) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * contracts: arm ladder-measured + ladder-green shapes for 0.68.2; contracts.nt regenerated with the two 0.68.2 ladder receipts as focus nodes (ONT-4c1, paiml#3508) Pmat-Ticket: PMAT-3477 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * CHANGELOG 0.68.2: rows for paiml#3533, paiml#3534 (merged since the cut) Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * CHANGELOG 0.68.2: row for paiml#3528 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * CHANGELOG 0.68.2: rows for paiml#3526, paiml#3530 (merged-since-tag predicate now 0) Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> * CHANGELOG 0.68.2: row for paiml#3536 Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> --------- Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Co-authored-by: Alfredo Deza <alfredo@deza.pe>
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Closes #3090.
Operator decision 2026-09-19 (in-session, verbatim selection): "GPU required — build #3090 now". This PR is the GPU half of the 0.68.2 interrupt (EPIC #3477); the CPU half landed in #3484.
What lands
crates/aprender-gpu/src/kernels/gdn/(causal conv1d+SiLU, per-head L2 norm, dt/β gates, delta-rule recurrence, gated RMSNorm, sigmoid gate)Qwen35CudaModel: DeltaNet and attention layers op-for-op,forward_single, config-sized device state,download_layercuda, parity/ptx-map stop refusing it, quant whitelist judges the SSM tensors, SSM predicate names the hybrid pathapr run/chat/qaroute qwen35 to the GPU; F2 guard judges the hybrid against its own CPU forward (Serial probe); no silent CPU fallback; stale "GPU declined (#3090)" skip reasons removedapr run --gpu: CUDA backend line, "Paris";apr qa: ALL GATES PASSED, Golden Output + Throughput on the GPUTwo measured facts that shaped it
qwen35_cuda_the_parity_floor_is_the_cpu_references_own_activation_quantization) bites in both directions.Qwen35CudaModelpins the float variant (DP4A Q4K/Q6K GEMV profile is catastrophic through the Gated DeltaNet recurrence — Qwen3.5 on sm_89 needs the float MWV variant (PMAT-806 class) #3513 for the root cause).Measured on lambda-vector (RTX 4090), pinned binary
gx10 (GB10) + ladder receipts: peer session runs both hosts at b2bd0c5; receipts land with the bump PR (#3498).
Process
Design grill 3/3 (refute-as-written → all four blocker classes applied: head_dim 256, partial rope, F2 reference, lockstep refusal sites). Pre-merge review quorum: in flight (docs/audits/quorum-PMAT-3477-pr.json to follow). Workers: G, H, I, J, J2, J3, K1, K2, K3 — every acceptance re-run by the orchestrator.
ont-delta: none this PR adds device kernels and a GPU forward; no ontology type, shape, reason or resolution changed
🤖 Generated with Claude Code
Issue refs (§6 R-2)
keep-open: #3477 — the release epic closes at the tag, not at this PR.
keep-open: #3513 — DP4A-through-recurrence root cause (0.69.0), mitigated here by pinning the float GEMV.
keep-open: #3346 #3510 — dense sizes 4B/9B/27B: the GQA-in-GDN CPU fix rides this branch; the CUDA half and the size rungs follow.
Two-host ladder at b2bd0c5 (peer session, main contract overlaid)
~/probe/receipts-b2bd0c5dc-mainladder/gx10.json/home/noah/probe/receipts-b2bd0c5dc-mainladder/lambda.json