[PW_SID:1142914] drm/spacemit: add SpacemiT K3 display support - #2436
[PW_SID:1142914] drm/spacemit: add SpacemiT K3 display support#2436linux-riscv-bot wants to merge 17 commits into
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Document the Saturn display processing unit found on the SpacemiT K3 SoC. The K3 instantiates two of them, one per display path. They share a compatible: an instance differs only in which register window, interrupt, clock and reset lines it takes. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The SpacemiT K3 DisplayPort controller drives its four transmit lanes through an integrated Innosilicon DP PHY, one PHY per controller. Add a binding so the controller can reference its transmit PHY and the pixel clock the PHY's PLL sources. The PHY's registers are interleaved with its parent controller's inside one MMIO window, so it owns neither a reg nor a reset and is modelled as a child of the controller. It exposes its PLL-generated pixel clock through #clock-cells, so the APMU pixel-clock mux can select it as a parent through the clock framework. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Both K3 instances are the same IP and share one compatible; which one behaves as eDP is decided by what its downstream port is wired to, not by which register window it sits in, so the binding does not distinguish them. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The APMU's eDP pixel-clock muxes select the DP PHY PLLs as parents, so the K3 syscon takes two clock inputs the other variants do not have. Gate them behind the K3 compatible instead of widening the shared clock list, so a non-K3 syscon cannot silently accept clocks it has no mux for. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The PHY's registers are interleaved into its parent DP controller's MMIO window rather than a window of its own, so it probes as a child of the controller, carries no reg or reset, and reaches its registers through the controller's regmap. It registers its pixel PLL as a clock provider. That lets the display controller ask for a mode's pixel rate through clk_set_rate(), and it lets the APMU pixel-clock mux parent to the PHY through the clock framework. Without it the controller and PHY would have to know each other's registers. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The APMU eDP/DP pixel-clock muxes were parented to a placeholder, because their real parents (the DP PHY PLLs) did not exist as clocks yet. They do now, so point each mux at its PLL and let the pixel clock reach the controller through the clock framework. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The Saturn display processing unit is programmed through a set of register blocks (composer, RDMA, timing generator, cmdlist engine, display MMU) laid out identically in both SoC instances. Add the block address map, the per-field word offset and mask tables consumed by the field accessors, the interrupt bit layout and the compositor and output-format ID encodings. The address map describes the whole IP block on purpose, including blocks the driver does not touch; the field tables carry the fields the driver programs, with each block's full word count kept as its NWORDS extent. Consumers arrive with the following patches; the driver only becomes buildable once the final patch adds the Kconfig and Makefile glue. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Register programming of the Saturn DPU is batched: the driver builds per-module register lists in memory and the hardware command-list engine replays them at frame boundaries, while scanout buffers are mapped through the DPU's private address translation unit (DMMU) rather than scanned out by physical address. Add the shared driver types, the MMIO field accessors, the trace events, the command-list builder and the DMMU table code. Some DPU configuration registers are write-only, so a read-modify-write would corrupt neighbouring fields; byte- and halfword-aligned fields are therefore written at their native width instead. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the register-level programming of one Saturn instance: clock and reset bring-up, scene control and timing generator setup, RDMA channel and composer layer programming, FBC line-buffer budgeting, interrupt dispatch and the cfg-ready/vsync handshake that paces commits. The backend is exposed as an ops table and hardware descriptor to be aggregated by the KMS layer in an upcoming patch. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the atomic KMS implementation on top of the hardware backend: one CRTC and one primary plane per DPU instance. atomic_check validates the plane rectangle 1:1 against the mode and sizes the per-channel FBC line buffer; atomic commit builds the cmdlist batches, maps the framebuffer through the DMMU and arms the cfg-ready handshake, with vblank events driven from the DPU interrupt. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the DRM device for the SpacemiT K3 Saturn display processing unit and hook the driver up to the build. The SoC has two DPU instances; each drives one CRTC that scans out a single primary plane in linear RGB at up to 3840x2160@60 and feeds a downstream DP/eDP controller over an OF-graph endpoint. Buffers use drm_gem_shmem_helper. The AFBC/compressed decode path is not exposed and writeback is not implemented. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the DP/eDP controller that sits downstream of the Saturn DPU. Two identical instances share one compatible; the eDP-vs-DP role is board wiring, so it is taken from the devicetree: an eDP panel always sits under an aux-bus child node, an external DP connector never does. The link is driven through the generic PHY framework, so the controller never touches a PLL register. The controller's HPD interrupt is gated by the DP pixel clock, which can be off exactly when a plug has to be caught, so the connector is also polled and the interrupt path re-reads the live level when it does fire. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Cover the Saturn DPU, the Innosilicon DP/eDP controller, the DP PHY and their bindings. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the SoC-level display nodes: the two Saturn DPUs, the two DP/eDP controllers with their PHY children. The PHY PLLs are fed back into the APMU as pixel-clock mux parents, so updated the &syscon_apmu node in the display dtsi. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Pico-ITX brings the second DPU's output to an external DisplayPort connector. Enable that DPU and the DisplayPort controller it feeds. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
CoM260-IFX carries a single DisplayPort output, so the second DPU and the DisplayPort controller it feeds are enabled. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Enable the Saturn DPU and the DP/eDP controller as modules, matching the other DRM drivers in this defconfig; the DP PHY follows through the controller's imply. Signed-off-by: Cody Kang <codykang.hk@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 1: "[v2,01/17] dt-bindings: display: spacemit: add K3 Saturn DPU controller" |
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Patch 2: "[v2,02/17] dt-bindings: phy: add SpacemiT K3 Innosilicon DP PHY" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 15: "[v2,15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 16: "[v2,16/17] riscv: dts: spacemit: k3-com260-ifx: enable the DisplayPort output" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
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Patch 17: "[v2,17/17] riscv: defconfig: spacemit: k3: enable display driver" |
PR for series 1142914 applied to workflow__riscv__fixes
Name: drm/spacemit: add SpacemiT K3 display support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1142914
Version: 2