The pre-synthesis structural diagnostic engine that catches timing bottlenecks in milliseconds.
Traditional FPGA and ASIC design flows suffer from massive feedback latency. You make a 1-line RTL change, wait 20 minutes for physical placement and routing, only to realize you failed setup time because your logic depth was 35 gates deep.
ConstraintForge shifts structural timing closure entirely to the left. It bypasses physical synthesis, extracts your Abstract Syntax Tree (AST), and runs a Topological DFS to find your exact setup-time, CDC, and fanout bottlenecks in under 100 milliseconds.
Read the Documentation | Timing Calculator | AI Generator
ConstraintForge invokes headless Yosys to parse your Verilog into a Directed Acyclic Graph (DAG). Because it operates strictly on the gate topology rather than physical routing, the algorithm scales deterministically at
- Setup-Time Risks: Calculates exact logic depth between registers.
- CDC Violations: Maps clock domains and traps unsynchronized crossings (missing 2FFs).
- Fanout Bottlenecks: Flags nets driving >100 loads so you can insert buffer trees early.
- Source-Code Back-Annotation:** Maps hazards directly to your exact
.vline numbers.
Install the CLI globally via pip:
pip install constraintforge(Requires yosys installed and available in your $PATH. Run brew install yosys on macOS or apt-get install yosys on Linux).
Run the diagnostic engine on any Verilog or SystemVerilog top module:
constraintforge diagnose rtl/picorv32.v --top picorv32ConstraintForge was benchmarked against Vivado's out-of-context (OOC) Synthesis/STA engine. ConstraintForge's pre-synthesis structural depth predictions were validated 1-to-1 against Vivado's physical post-route STA. It successfully finds the exact same critical logic bottlenecks while running 83x to 600x faster.
| Design | Physical LUTs | Vivado STA (s) | ConstraintForge (s) | Speedup | Physical Delay (ns) |
|---|---|---|---|---|---|
| picorv32 | 933 | 20.0 | 0.08 | 250x | 4.744 |
| aes_core | 266 | 11.0 | 0.04 | 275x | 6.303 |
| darkriscv | 144 | 10.0 | 0.03 | 333x | 3.857 |
| ibex_core | 124 | 11.0 | 0.03 | 366x | 4.102 |
| VexRiscv | 94 | 10.0 | 0.03 | 333x | 3.309 |
| i2c_master | 27 | 11.0 | 0.02 | 550x | 2.668 |
| spi_master | 21 | 12.0 | 0.02 | 600x | 2.418 |
| fetch_unit (riscv-ooo) | 11 | 10.0 | 0.12 | 83x | 2.980 |
ConstraintForge originally began as an open-source library of highly annotated .xdc, .sdc, and .lpf timing constraint templates. Those templates are still heavily maintained in this repository.
The official vendor docs are spread across Xilinx UG903, Intel AN433, and Stack Overflow answers from 2013. The interfaces/ and boards/ directories in this repo put everything in one place — constraint templates for every interface (SPI, I2C, DDR3, RGMII, MIPI), annotated so you understand what each line does.
You can browse the library visually on our Interactive Website.
Whether you are adding a new diagnostic rule to the CLI Python engine, or submitting a new board constraint file, PRs are welcome. See CONTRIBUTING.md.
MIT.