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Port to Chisel 7 with Scala 3 - #84
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| parameter bit RESET_ASYNC = 1'b1 | ||
| parameter logic [WIDTH-1:0] INIT = '0 |
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When RegNegNext or RegNegEnable is instantiated with an initialization value, the emitted design includes this resource, but the missing comma after RESET_ASYNC = 1'b1 makes the SystemVerilog parameter list invalid. Any HDL compiler processing Chipmunk_RegNegInit will therefore reject the generated design before simulation or synthesis; add a comma between RESET_ASYNC and INIT.
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Hold arbiter and external routing selections under backpressure. Add transaction-paired selection tokens, independent broadcast forks, typed joins, Flow fan-out, and a Chisel Queue adapter. Document the Stream protocol and migrated APIs. Add component simulations and pass all 46 Stream/Flow regression tests with the branch's Scala 3.8.4 and Chisel snapshot dependencies.
Introduce chipmunk.acorn IO, Mux, Demux, Crossbar, and ErrorPoint with configurable address maps, local address translation, and ordered responses. Keep shared routing logic private and split configuration from components. Split Acorn tests into Config, Mux, Demux, and Crossbar specs with shared test helpers. Update Acorn documentation for the current protocol, package, configuration, and timing constraints. Validation: strict Acorn and test compilation, six passing Acorn tests, and scalafmt checks.
Use a per-field Bool for write-once locking, and exclude zero-mask and locked software writes from update arbitration. Keep hardware assignments available after a software write-once lock. Add pure Scala configuration with BigInt reset values and local byte offsets. Validate names, addresses, field ranges, reset values, and field IO aliases. Implement field IO with Record and retain the three-argument RegBank constructor and existing field keys. Add configuration and protocol regression tests, shorten Scaladoc, and document byte addressing, response timing, and collision semantics. Validation: strict RegBank and test compilation, scalafmt checks, and all 86 Chipmunk tests passing (including 12 new RegBank tests).
Group EmptyBundle and MapBundle in Bundles.scala. Validate nonempty, unique keys and clone unbound field types while preserving their order, widths, and directions. Refactor RegBankFieldIO to use MapBundle while retaining existing field lookup aliases. Add tests for template reuse, IO flips, aggregate cloning, invalid fields, and empty Stream payloads. Validation: strict changed-source and test compilation, scalafmt checks, and all 16 Bundles/RegBank tests passing.
Support byte-masked 1RW and 1R1W SRAM interfaces with reserved read-response capacity and ordered responses. Add asynchronous-reset, backpressure, arbitration, and throughput tests, and document the SRAM backend requirements. Validation: all 111 Chipmunk tests pass; strict adapter and test compilation and Scalafmt checks pass.
Add two-entry read and write command queues without flow or pipe bypass. Derive SRAM control from buffered commands and local state, and reserve response capacity at bus acceptance so outstanding limits also cover queued commands. Update latency and arbitration checks, verify bus isolation and response backpressure, and ensure asynchronous reset cancels queued accesses without undoing committed writes. Document the extra command cycle and capacity accounting. Validation: all 115 Chipmunk tests pass, including 25 SRAM tests; strict adapter and test compilation, Scalafmt, and whitespace checks pass.
Adapt the current AXI interfaces with fixed IDs and single-beat fields, without buffering or added channel latency. Check response IDs, RLAST, and unexpected EXOKAY responses. Add ChipmunkFlatSpec coverage for 32/64-bit transfers, optional fields, both AW/W arrival orders, independent stalls, and parameter validation.
Add full-width AXI-to-Acorn burst conversion and single-beat Acorn-to-AXI and Acorn-to-AXI-Lite bridges with independent read/write control. Add AcornWidthAdapter with registered transactions, byte-lane conversion, and first-error termination. Document read-footprint and split-access requirements without adding resizing permission switches. Add ChipmunkFlatSpec coverage for independent handshakes, backpressure, bursts, byte masks, error responses, and parameter validation.
Move AcornParams and AcornOutstanding into AcornIO.scala. Move arbitration, slave address windows, and crossbar configuration into AcornCrossbar.scala, and remove AcornConfig.scala. Rename AcornParams.bytesPerWord to strobeWidth throughout adapters, RegBank configuration, Specs, and the Acorn documentation.
Add Seq[Bool] and Bits overloads in MuxPriority.scala, returning the explicit default when no input is asserted. Use 7.16.0+3-a2d66312-SNAPSHOT for both the Chisel library and compiler plugin while retaining Scala 3.8.4.
Add SpiIO and SpiDebugger under chipmunk.spi, preserving the command encodings and register indices while adapting accesses to the byte-addressed RegBank. Snapshot requests, serialize bus transactions, and expose completion and rejection status. Return 0xDEAD_BEEF for an early fast read while retaining late responses for polling. Handle incomplete frames and address errors. Document the 8:1 system/SCK clock requirement and add 11 passing simulation tests covering all SPI modes, clock phases, backpressure, late and same-cycle responses, aborted frames, address widths, and reset.
Update the README and reference pages to match the current APIs and behavior. Add documentation for state machines, reset synchronization, AMBA bridges, flat RTL ports, and ChiselSim helpers. Document Acorn width adaptation and register-field access rules. Keep installation instructions focused on Mill. Set the publish version to 0.2.0-SNAPSHOT. Omit the Scala 3 migration guide and Scala 2 maintenance discussion. Validation: compile 44 documentation excerpts, elaborate 42 hardware examples, and check all 56 internal documentation links.
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