A two-stage 16-bit CPU implementation in Verilog HDL, featuring datapath design, ALU, register files, memory integration, and a hardwired control unit. Developed for the BLG222E Computer Organization course at Istanbul Technical University.
Architecture diagram from the BLG222E Computer Organization project specification, included for educational and documentation purposes.
This repository contains the implementation of a simple 16-bit CPU developed in two consecutive projects.
- 16-bit Register
- Instruction Register (IR)
- Register File
- Address Register File (ARF)
- Arithmetic Logic Unit (ALU)
- Datapath Integration
- System Simulation
- Hardwired Control Unit
- Instruction Fetch
- Instruction Decode
- Instruction Execution
- Memory-based Program Execution
- CPU Simulation
- Verilog HDL
- Vivado
- Digital Logic Design
- Computer Organization
Project1_CPU_Components/
Project2_Control_Unit/
docs/
This project was developed collaboratively by:
- Zeynep Nur Yılmaz
- Nejra Gutić
as part of the BLG222E Computer Organization course.
This repository is shared for educational and portfolio purposes. Project specifications and some simulation files were provided as part of the course.