STM32N6: Fix PLL1 600 MHz clock, code cleanup, add release doc

  Fix PLL1 bypass bit (PLL1BYP) in PLL1CFGR1 that Boot ROM leaves set,
  which was routing HSI 64 MHz directly to PLL output instead of the
  1200 MHz VCO. CPU now runs at 600 MHz (verified via DWT CYCCNT).

  - Clear PLL1CFGR1 BYP bit to enable VCO output
  - Simplify PLL1CFGR3 configuration to single write
  - Consolidate flash write/erase into shared nor_flash_write/erase helpers
  - Rename xspi_ functions to octospi_ for consistency with register macros
  - Add CORTEX_M55 define to arch.mk for future use
  - Add clock tree documentation in clock_config() and PWR_VOSCR
  - Combine CPUSW and SYSSW clock switch into single register write
  - Add XSPI2 RAMFUNCTION comments and TEF error handling
  - Add release announcement doc (docs/release-stm32n6.md)
  - wolfBoot binary: 23KB, test-app: 3KB

Author: aidangarske

arch.mk

@@ -364,7 +364,7 @@ else
   endif
   ifeq ($(CORTEX_M55),1)
     CORTEX_M33=1
-    CFLAGS+=-mcpu=cortex-m55
+    CFLAGS+=-mcpu=cortex-m55 -DCORTEX_M55
     LDFLAGS+=-mcpu=cortex-m55
   endif
   ifeq ($(CORTEX_M33),1)