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Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q)
 Add HAL, build system, test app, and documentation for the STM32N6 (Cortex-M55) targeting the NUCLEO-N657X0-Q board. wolfBoot runs from SRAM as FSBL and boots a signed application via XIP from external NOR flash on XSPI2.
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‎.github/workflows/test-configs.yml‎

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@@ -473,6 +473,12 @@ jobs:
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arch: arm
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config-file: ./config/examples/stm32h5-tz-dualbank-otp-lms.config
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stm32n6_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32n6.config
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stm32h7_test:
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uses: ./.github/workflows/test-build.yml
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with:

‎Makefile‎

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@@ -274,6 +274,11 @@ ifeq ($(TARGET),sama5d3)
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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ifeq ($(TARGET),stm32n6)
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# wolfBoot runs from SRAM, app from XIP on external NOR - no contiguous factory.bin
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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ifeq ($(TARGET),rp2350)
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MAIN_TARGET:=include/target.h keytools wolfboot_signing_private_key.der pico-sdk-info
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endif
@@ -653,6 +658,12 @@ stack-usage: wolfboot.bin
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image-header-size: wolfboot.bin
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$(Q)echo $(IMAGE_HEADER_SIZE) > .image_header_size
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## Target-specific flash targets
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ifeq ($(TARGET),stm32n6)
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flash: wolfboot.bin test-app/image_v1_signed.bin
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$(Q)tools/scripts/stm32n6_flash.sh --skip-build
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endif
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cppcheck:
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cppcheck -f --enable=warning --enable=portability \

‎arch.mk‎

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endif
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ifeq ($(TARGET),stm32n6)
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CORTEX_M55=1
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CFLAGS+=-Ihal
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ARCH_FLASH_OFFSET=0x70000000
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WOLFBOOT_ORIGIN=0x34000000
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EXT_FLASH=1
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PART_UPDATE_EXT=1
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PART_SWAP_EXT=1
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endif
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ifeq ($(TARGET),rp2350)
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CORTEX_M33=1
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CFLAGS+=-Ihal
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CORTEXM_ARM_EXTRA_CFLAGS+=-DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO \
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-DWOLFSSL_ARMASM_NO_NEON -DWOLFSSL_ARMASM_THUMB2
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endif
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ifeq ($(CORTEX_M55),1)
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CORTEX_M33=1
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CFLAGS+=-mcpu=cortex-m55
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LDFLAGS+=-mcpu=cortex-m55
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endif
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ifeq ($(CORTEX_M33),1)
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CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
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LDFLAGS+=-mcpu=cortex-m33
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CFLAGS+=-DCORTEX_M33
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ifneq ($(CORTEX_M55),1)
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CFLAGS+=-mcpu=cortex-m33
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LDFLAGS+=-mcpu=cortex-m33
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endif
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ifeq ($(TZEN),1)
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ifneq (,$(findstring stm32,$(TARGET)))
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OBJS+=hal/stm32_tz.o

‎config/examples/stm32n6.config‎

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ARCH?=ARM
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TARGET?=stm32n6
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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NO_ASM?=0
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NO_MPU=1
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=1
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V?=0
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SPMATH?=1
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RAM_CODE?=0
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_PARTITION_SIZE?=0x100000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x70020000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x00120000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x00010000
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IMAGE_HEADER_SIZE?=1024

‎config/openocd/openocd_stm32n6.cfg‎

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# OpenOCD config for NUCLEO-N657X0-Q with MX25UM51245G NOR on XSPI2
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source [find interface/stlink.cfg]
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transport select swd
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set CHIPNAME stm32n6x
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set WORKAREASIZE 0x10000
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source [find target/stm32n6x.cfg]
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# Work-area above wolfBoot SRAM region
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$_TARGETNAME configure -work-area-phys 0x34020000 -work-area-size $WORKAREASIZE -work-area-backup 0
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# XSPI2 NOR flash bank (memory-mapped at 0x70000000, regs at 0x5802A000)
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set XSPI2_BANK_ID [llength [flash list]]
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flash bank $CHIPNAME.xspi2 stmqspi 0x70000000 0 0 0 $CHIPNAME.cpu 0x5802A000
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# Mark VDDIO supplies valid (required for XSPI2 GPIO)
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proc pwr_enable_io_supply {} {
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mmw 0x5602825C 0x00040000 0 ;# RCC_AHB4ENR: PWR clock
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mmw 0x56024834 0x00000100 0 ;# SVMCR1: VDDIO4SV
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mmw 0x56024838 0x00000100 0 ;# SVMCR2: VDDIO5SV
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mmw 0x5602483C 0x00000300 0 ;# SVMCR3: VDDIO2SV + VDDIO3SV
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}
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# Port N GPIO for XSPI2 (PN0-PN11, AF9, very high speed)
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proc xspi2_gpio_init {} {
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mmw 0x5602825C 0x00002000 0 ;# RCC_AHB4ENR: GPION clock
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sleep 1
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mmw 0x56023400 0x00AAAAAA 0x00555555 ;# MODER: AF mode
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mmw 0x56023408 0x00FFFFFF 0 ;# OSPEEDR: very high
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mmw 0x5602340C 0 0x00FFFFFF ;# PUPDR: no pull
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mww 0x56023420 0x99999999 ;# AFRL: AF9
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mww 0x56023424 0x00009999 ;# AFRH: AF9
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}
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# XSPI2 init: single-SPI, /16 prescaler, NOR reset, enter mmap mode
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proc xspi2_init {} {
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mmw 0x56028260 0x00003000 0 ;# RCC_AHB5ENR: XSPI2 + XSPIM clocks
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mmw 0x56028248 0x00000008 0 ;# RCC_MISCENR: XSPI PHY comp clock
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sleep 1
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mww 0x5802A000 0x00000000 ;# CR: disable
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sleep 1
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mww 0x5802A008 0x001A0308 ;# DCR1: DLYBYP, DEVSIZE=26, CSHT=3
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mww 0x5802A00C 0x0000000F ;# DCR2: prescaler /16
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sleep 1
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mww 0x5802A000 0x00000001 ;# CR: enable
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# NOR flash software reset (0x66 + 0x99)
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A024 0x0000000B ;# FCR: clear flags
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mww 0x5802A100 0x00000001 ;# CCR: IMODE=single
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mww 0x5802A108 0x00000000 ;# TCR: no dummy
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mww 0x5802A110 0x00000066 ;# IR: Reset Enable
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sleep 1
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A024 0x0000000B
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mww 0x5802A100 0x00000001
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mww 0x5802A108 0x00000000
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mww 0x5802A110 0x00000099 ;# IR: Reset Memory
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sleep 10
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xspi2_mem_mapped
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}
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# Memory-mapped fast-read mode (single-SPI, 4-byte addr, 8 dummy cycles)
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proc xspi2_mem_mapped {} {
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A000 0x30000001 ;# CR: mmap + enable
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mww 0x5802A100 0x01003101 ;# CCR: IMODE=1, ADMODE=1, ADSIZE=3, DMODE=1
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mww 0x5802A108 0x40000008 ;# TCR: DCYC=8, SSHIFT
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mww 0x5802A110 0x0000000C ;# IR: Fast Read 4B
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}
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# Set NOR flash params manually (SFDP not readable in single-SPI mode)
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proc xspi2_flash_set {} {
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global XSPI2_BANK_ID
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stmqspi set $XSPI2_BANK_ID MX25UM51245G 0x4000000 0x100 0x13 0 0x12 0x60 0x1000 0x21
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}
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# Full reinit for use when XSPI2 may already be configured
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proc xspi2_reinit {} {
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global XSPI2_BANK_ID
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pwr_enable_io_supply
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xspi2_gpio_init
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xspi2_init
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xspi2_flash_set
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flash probe $XSPI2_BANK_ID
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xspi2_flash_set
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}
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$_TARGETNAME configure -event reset-init {
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global XSPI2_BANK_ID
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pwr_enable_io_supply
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xspi2_gpio_init
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xspi2_init
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xspi2_flash_set
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flash probe $XSPI2_BANK_ID
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# Re-set after probe (stmqspi driver quirk)
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xspi2_flash_set
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}
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init

‎docs/Targets.md‎

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* [STM32F7](#stm32f7)
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* [STM32G0](#stm32g0)
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* [STM32H5](#stm32h5)
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* [STM32N6](#stm32n6)
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* [STM32H7](#stm32h7)
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* [STM32L0](#stm32l0)
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* [STM32L4](#stm32l4)
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```
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## STM32N6
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The STM32N6 (Cortex-M55) has no internal flash — all firmware resides on external
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NOR flash (Macronix MX25UM51245G, 64MB) connected via XSPI2. The on-chip Boot ROM
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copies the FSBL (First Stage Boot Loader) from external flash to internal SRAM and
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jumps to it. wolfBoot serves as the FSBL, performing image verification and
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chain-loading the application from external flash in XIP (Execute-In-Place) mode.
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Tested on: **NUCLEO-N657X0-Q** (STM32N657X0H, MB1940)
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### Memory Layout
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```
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XSPI2 NOR Flash (memory-mapped at 0x70000000):
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0x70000000 FSBL header area (128KB, future autonomous boot)
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0x70010000 Swap partition (64KB, device-relative: 0x00010000)
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0x70020000 Boot partition (1MB, app runs from here via XIP)
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0x70120000 Update partition (1MB, device-relative: 0x00120000)
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AXISRAM (0x34000000):
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0x34000000 wolfBoot (loaded to SRAM via SWD or Boot ROM FSBL copy)
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0x34020000 Stack / work area
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```
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### Build and Flash
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Use the example configuration and build:
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```sh
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cp config/examples/stm32n6.config .config
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make
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make flash
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```
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`make flash` uses OpenOCD with the stmqspi driver to:
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1. Program the signed application to NOR flash at 0x70020000
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2. Load wolfBoot to SRAM at 0x34000000
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3. Start wolfBoot, which verifies and boots the application via XIP
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Prerequisites:
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- OpenOCD 0.12+ with stm32n6x target support (build from source if needed)
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- ST-Link connected to the Nucleo board
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- arm-none-eabi toolchain in PATH
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### Build Options
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```sh
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make TARGET=stm32n6 SIGN=ECC256
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```
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The example config uses:
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- `EXT_FLASH=1` with `PART_UPDATE_EXT=1` and `PART_SWAP_EXT=1`
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- Boot partition at 0x70020000 (XIP, not marked EXT)
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- Update/swap partitions use device-relative offsets
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- 4KB sector size (`WOLFBOOT_SECTOR_SIZE=0x1000`)
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- ECC256 + SHA256 for signature verification
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### XIP Constraints
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Since the application executes directly from NOR flash via XSPI2 memory-mapped
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mode, the following constraints apply:
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- The application must NOT call `hal_init()` — XSPI2 is already configured by
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wolfBoot for memory-mapped mode. Reinitializing XSPI2 would disable XIP and
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crash the CPU.
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- Calling `wolfBoot_success()` requires all flash write functions to be placed
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in RAM (RAMFUNCTION). The HAL flash functions in `hal/stm32n6.c` need the
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RAMFUNCTION attribute for this to work from an XIP application.
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### Flash Script Options
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The flash script supports several modes:
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```sh
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./tools/scripts/stm32n6_flash.sh # Build and flash all
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./tools/scripts/stm32n6_flash.sh --skip-build # Flash only (existing binaries)
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./tools/scripts/stm32n6_flash.sh --app-only # Flash signed app only
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./tools/scripts/stm32n6_flash.sh --test-update # Flash v1 boot + v2 update
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./tools/scripts/stm32n6_flash.sh --halt # Leave OpenOCD running
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```
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### Debugging
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OpenOCD:
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```sh
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openocd -f config/openocd/openocd_stm32n6.cfg
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```
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After OpenOCD starts, connect via telnet (port 4444). To manually load wolfBoot
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and start it:
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```sh
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reset halt
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load_image wolfboot.bin 0x34000000 bin
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reg msplim_s 0x00000000
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reg psplim_s 0x00000000
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reg msp 0x34020000
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mww 0xE000ED08 0x34000000
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resume <entry_address>
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```
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The entry address can be found with:
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```sh
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arm-none-eabi-nm wolfboot.elf | grep isr_reset
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```
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GDB:
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```sh
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arm-none-eabi-gdb wolfboot.elf
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target remote :3333
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mon halt
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add-symbol-file test-app/image.elf 0x70020400
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```
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## STM32H7
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The STM32H7 flash geometry must be defined beforehand.

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