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Hardware validation of PR #767 on Radeon RX 9060 XT 16 GB ( Environment:
I explicitly forced the scalar F32 routes with:
This prevents the validation from passing by routing around the changed scalar code through WMMA. Scalar Q8 boundary matrix
All cases exited successfully. No Native-MTP serve batteryCommitted
Long-context native-MTP testThe 16K-configured NIAH case completed through the forced scalar route:
32K caveatThe original 32K-configured NIAH fixture could not complete on this 16 GB board. After the native MTP sidecar loaded and the MTP speculator was enabled, prefill stopped with:
This was an allocation failure, not the previous:
Therefore I cannot claim complete end-to-end validation of the exact original 32K fixture on this GPU. However, the scalar boundary matrix, committed native-MTP battery, and successful 10.9K-token native-MTP prefill all confirm that batches above 64 are now chunked successfully on Verdict:
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Summary
Fixes #732 by routing scalar Q8 native-MTP batches through the existing F32
chunked entry point, which splits the batch dimension at the kernel's fixed
MAX_BATCH=64boundary.This preserves the scalar F32 reduction contract while allowing Qwen3.8 native
MTP prefill and verification widths such as 65, 70, 76, and 256 to complete
instead of failing at runtime.
Root cause and fix
gemm_q8_0_batchedis a fixed-size scalar kernel and correctly rejectsbatch_size > 64. Beta already providesgemm_q8_0_batched_f32_chunked, but several native-MTP scalar-Q8 surfacesstill called the fixed-size kernel directly.
This change routes those surfaces through the existing chunked entry point:
bench_q8_0_batched.The scalar kernel and automatic WMMA selector are unchanged. Batches at or
below 64 retain the existing behavior; wider batches become contiguous chunks,
for example
70 = 64 + 6and256 = 4 x 64.Closes #732.
Which surface(s) does this touch?
crates/rdna-computehipfire-arch-qwen35crates/hipfire-quantize/ quant formatsTest plan
./scripts/no-gpu-ci.shpasses, or the CI jobs are greencargo build --release --workspace --all-targets --lockedcargo test -p hipfire-arch-qwen35 --lib— 196 passed, 17 ignoredcargo test -p rdna-compute --lib -- --skip dispatch::tests::upload_raw_copy_failure_hip_frees_owner— 244 passedserve_harness.py --mode battery— pending an uncontended GPU window; the first attempt was discarded because an unrelated hardware campaign began concurrentlyThe skipped allocator test compares process-global free VRAM for exact equality.
It passed three isolated repetitions, but failed inside the full crate once when
free VRAM decreased by 2 MiB and once when it increased by 4 MiB. This diff does
not touch allocation code; the result is disclosed as beta baseline flakiness.
Scalar-Q8 boundary matrix
Hardware: Radeon AI PRO R9700 (
gfx1201), ROCm/HIP 7.14. The legacy scalarroute was forced with
HIPFIRE_Q8_BATCHED_LEGACY=1.No
MAX_BATCHerror occurred.32K-output long-context quality evidence
Target:
qwen3.8-27b.mq4-xtTarget SHA-256:
9f91556f7e0431a077d03756a7102d0154108757289e6e5fe9a2d204c0c9eeb7Native Q8 MTP sidecar SHA-256:
c160bbf9f8cc4b9cee3bd3e8438263aec7946f661e2254ceecf9990ce86bd1d3Daemon MD5:
2aee0c769188beec3af9606a9ab79bfbConfiguration: Q8 VMM KV,
max_seq=65536, greedy, thinking off, native MTPenabled, scalar-Q8 route forced, maximum output 32,768 tokens.
LongBench-v2 hard30:
finish_reason=stop;MAX_BATCHfailures;This is a single-arm supplementary quality smoke test, not an accuracy-equivalence
or performance claim.
Five long-decode prompts:
All five requests completed without runtime errors, empty output, or a repetition
attractor. The automated repetition heuristic flagged code/table/formula patterns;
manual inspection found structured repetition rather than decoding collapse. The
Snake syntax defect is retained in the report as model-output quality evidence,
not hidden as a pass.
local serve_harness battery.json
Pending an uncontended post-rebase hardware run. This draft will not be marked
ready until the complete per-turn JSON is attached.
Hardware validation request
{ "routes": [ {"mode": "battery", "tag": "qwen3.8:27b"} ], "claim": "native Qwen3.8 MTP scalar-Q8 batches above 64 rows complete without a MAX_BATCH runtime failure" }Architecture-trait change?
No.