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No clock signals being traced inside testbench module

Status: Open.

#133 In vproc/vicuna;

· pah69 opened on Mar 12, 2026

How to handle "30525: Illegal instruction (hart 0) at PC 0x0000208c: 0x304022f3"?

Status: Open.

#123 In vproc/vicuna;

· deeplearner92 opened on Sep 12, 2024

How to Handle conv + bias in conv_3x3 for input(int8) * weight(int8) + bias(int32)?

Status: Open.

#122 In vproc/vicuna;

· Haleski47 opened on Jul 30, 2024

Applications hang indefinitely on Verilator when size of data cache is different than 0

Status: Open.

#121 In vproc/vicuna;

· maheshejs opened on Jan 4, 2024

Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely

Status: Open.

#119 In vproc/vicuna;

· AnjaliVerma1314 opened on Nov 28, 2023

Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model

Status: Open.

#118 In vproc/vicuna;

· AnjaliVerma1314 opened on Nov 28, 2023

Error in Questasim Simulation

Status: Open.

#114 In vproc/vicuna;

· aaqdas opened on Jul 26, 2023

'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8

Status: Open.

#112 In vproc/vicuna;

· ParkerJones567 opened on Jul 3, 2023

Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core

Status: Open.

#111 In vproc/vicuna;

· Nikhil-311293 opened on May 5, 2023

Floating point support.

Status: Open.

#110 In vproc/vicuna;

· Nikhil-311293 opened on Mar 16, 2023

No way to clear a cache error?

Status: Open.

#105 In vproc/vicuna;

· stevobailey opened on Sep 24, 2022

Vicuna + Ibex and WFI

Status: Open.

#104 In vproc/vicuna;

· stevobailey opened on Aug 11, 2022