cpu: rv64: reuse xf16 softmax strided JIT kernels - #5980
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Use process-wide gather/scatter kernels and retain non-owning pointers only for non-contiguous xf16 softmax primitives. Assisted-by: OpenCode:deepseek-v4-pro [yuansheng-kit]
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hi zhangjian (@zhangjian29), this PR is ready for review. If it looks good, could you please approve it? |
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Thanks for the reminder @ww8191201-coder |
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cpu: rv64: reuse shared xf16 softmax strided JIT kernels
Description
The RV64 non-contiguous f16/bf16 softmax path invokes gather and scatter kernels once for every softmax block. The existing dispatcher already keeps one function-local static JIT kernel for each direction, but every call still executes compiler-generated thread-safe-static guard bookkeeping in the hot path.
This PR exposes the existing shared gather/scatter kernels through
get_xf16_strided_kernel<>(), resolves them once when a relevant softmax primitive is created, stores non-owning pointers in the primitive, and invokes the kernels directly during execution. This removes the per-block dispatcher and static-guard overhead without generating JIT code for every primitive.The accessors are invoked only for f16/bf16 primitives with
inner_size > 1. For contiguous softmax the two pointer members remain null and no strided kernel initialization occurs, while all strided xf16 primitives share the same process-wide gather/scatter JIT code.Implementation details
get_xf16_strided_kernel<true/false>()owns the same two function-local static kernels used by the existing dispatcher.rvv_softmax_fwd_thas two non-owningconstpointer members that are initialized only for the non-contiguous f16/bf16 path.jit_generator_tor 256 KiB strided-kernel code buffer is allocated per primitive.Test batches
Performance was measured with the following shapes for both f16 and bf16, using
abc, axis 1, forward inference, and both softmax and logsoftmax:benchdnn --mode=P -v1 --engine=cpu --softmax \ --fix-times-per-prb=100 --perf-template=csv \ --batch=rvv_softmax_f16_strided_sweep.batch benchdnn --mode=P -v1 --engine=cpu --softmax \ --fix-times-per-prb=100 --perf-template=csv \ --batch=rvv_softmax_bf16_strided_sweep.batchPerformance evaluation
Lower execution time is better. Baseline and patched measurements used the same executable, runtime settings, thread counts, and CPU affinity.
The K3 A100 tests start in a fresh process that switches to the AI-core group before oneDNN or any RVV code runs. One-thread measurements are pinned to one core, and eight-thread measurements are pinned to the corresponding eight-core group. K3 was returned to its original 2.2 GHz X100 and 1.8 GHz A100 settings after testing.
Detailed performance results
The following tables list every measured case. The K3 bf16 logsoftmax rows use
ref:anyand are shown as unaffected controls. K1 bf16 cases are omitted because they are not supported by the available ISA.K1 / Muse Pi Pro
jit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhThe K1 f16 aggregate improves from 242.0643 ms to 213.5520 ms (+11.78%) at one thread and from 67.5386 ms to 58.2656 ms (+13.73%) at eight threads. Every one-thread case improves, with gains ranging from +2.46% to +18.46%. Nine of the twelve eight-thread cases improve,
512x256x8logsoftmax is effectively unchanged at -0.20%, and the other two cases change by -0.80% and -3.49%. The largest gains appear in shapes that execute many short gather/scatter operations, where eliminating repeated dispatcher and static-guard bookkeeping removes a larger fraction of the total work.K3 X100
jit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyThe X100 f16 aggregate improves by +11.06% at one thread and +17.33% at eight threads. Considering only the six bf16 softmax rows that use the changed JIT path, the aggregate improves from 71.5279 ms to 61.8173 ms (+13.58%) at one thread and from 14.5313 ms to 12.9125 ms (+11.14%) at eight threads. The improvement is strongest for shapes with smaller axis sizes and larger inner strides, matching the expected reduction in per-block dispatch overhead. The bf16 logsoftmax reference rows remain close to baseline and serve as controls.
K3 A100
jit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfhjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyjit:rvv_zvfbfwmaref:anyThe A100 f16 aggregate improves by +1.75% at one thread and +0.80% at eight threads. Considering only the six bf16 softmax rows that use the changed JIT path, the aggregate improves from 178.7549 ms to 167.5219 ms (+6.28%) at one thread and from 23.7474 ms to 23.3307 ms (+1.75%) at eight threads. Gains are most visible for the smaller-axis bf16 softmax shapes. The smaller overall A100 benefit is consistent with the per-block dispatch overhead accounting for a lower fraction of execution time with 1024-bit vectors.
Correctness validation
ctestpassed.