胡金 專案
Full-stack Driver Scheduling & Fleet Management System built with React.js, TypeScript, Node.js, Express.js, and MongoDB. Enables efficient driver-route management through assignment scheduling, availability validation, conflict detection, analytics dashboards, activity tracking, and real-time monitoring. Developed for the DRB Internship Program.
Verilog behavioral models of SR, D, JK, and T flip-flops with testbenches and simulation results.
SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.
Implements a hierarchical 1-to-16 demultiplexer using a 1x2 and two 1x8 demux blocks in Verilog. Directs a single input signal to one of 16 outputs based on select lines. Features: Hierarchical Verilog modules (1x2 and 1x8), Behavioral testbench for all 16 select combinations, Graph-based output verification
Web app interaktif untuk belajar gerbang logika dasar dan lanjutan (Sistem Digital).
Verilog implementation of a synchronous 4-bit up/down decade counter with asynchronous clear, load, and carry-out features. Also includes a 2-decade decimal counter design using two such counters cascaded together. Simulates counting up/down from 00 to 99 with load, increment, and clear operations.
SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.
A Secure Scratch-Card Based Digital Support System for Campaign Engagement
Add a description, image, and links to the digital-system topic page so that developers can more easily learn about it.
To associate your repository with the digital-system topic, visit your repo's landing page and select "manage topics."