ddr

this repository is for files releated ddr ram , sim v/sv files alse included.

will@20220921

Name		Name	Last commit message	Last commit date
4187mt8lsdt864hg		4187mt8lsdt864hg
ddr4_verilog_models		ddr4_verilog_models
sdram		sdram
JESD79-5_DDR5_Spec.pdf		JESD79-5_DDR5_Spec.pdf
Memory systems Cache DRAM Disk.pdf		Memory systems Cache DRAM Disk.pdf
README.md		README.md

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