Rollup of 21 pull requests#158795
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Before mingw-w64/mingw-w64@dbfdf80 mkstemp used by Binutils was not sufficiently collision resilient and that led to CI errors for us. Our new baseline mingw-w64 toolchain's Binutils are built using mingw-w64 with the fix: niXman/mingw-builds#682 So, we should be able to get rid of it.
Add a tier 3 bare-metal target for RV32IMFC cores that have hardware single-precision floating point (the `F` extension, `ilp32f` ABI) but no atomic (`A`) extension. This is `riscv32imafc-unknown-none-elf` minus the atomic extension, handled the same way `riscv32imc-unknown-none-elf` handles a no-`a` core: `+forced-atomics` lowers atomic load/store to plain load/store (sound on a single hart) while `atomic_cas = false` keeps RMW/CAS off, so no `lr.w`/`sc.w`/`amo*` are ever emitted and the target does not trap on a core without the `A` extension. Downstream crates use a critical-section polyfill (e.g. `portable-atomic`) for compare-and-swap. This combination has no builtin target today: cores that pair a hardware-float application core with no atomic extension otherwise need a custom target spec plus `-Zbuild-std` on nightly, which is unavailable on stable. The motivating hardware is the application core of vendor SoCs such as the HiSilicon WS63/BS2X family, but the target is vendor-neutral. Register the target, add it to the `targets-elf` assembly sanity test, and document it on the shared `riscv32-unknown-none-elf` platform-support page.
In many cases where we are flattening `option::IntoIter<I>`, we can use `into_flat_iter()` instead for a simpler implementation.
This reverts commit 5fad8a6.
This tool is part of the main workspace, so its own lock file is unused, and the file is clearly outdated for its current dependencies anyway.
Splitting assembling the return value over multiple let-bindings enables pedagogic discussion of each named let-binding. The `slice` arg was renamed to remove any chance of visual confusion with use of `core::slice` functions or "slice" per se.
This starts with `StatementKind` and `TerminatorKind`; they don't need hashing. That then allows the removal of the `Hash` impl of various other types.
Signed-off-by: Ajay Singh <ajaykripa8736968359@gmail.com>
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@bors r+ rollup=never p=5 |
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This was referenced Jul 5, 2026
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What is this?This is an experimental post-merge analysis report that shows differences in test outcomes between the merged PR and its parent PR.Comparing ea088e0 (parent) -> 4eb6253 (this PR) Test differencesShow 399 test diffsStage 0
Stage 1
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Additionally, 358 doctest diffs were found. These are ignored, as they are noisy. Job group index
Test dashboardRun cargo run --manifest-path src/ci/citool/Cargo.toml -- \
test-dashboard 4eb62535fc12dd1a63fd43a4173e224e79313c4d --output-dir test-dashboardAnd then open Job duration changes
How to interpret the job duration changes?Job durations can vary a lot, based on the actual runner instance |
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📌 Perf builds for each rolled up PR:
previous master: ea088e0a3d In the case of a perf regression, run the following command for each PR you suspect might be the cause: |
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Successful merges:
riscv32imfc-unknown-none-elfbare-metal target #158473 (Addriscv32imfc-unknown-none-elfbare-metal target)src/tools/test-float-parse/Cargo.lock#158669 (Removesrc/tools/test-float-parse/Cargo.lock)split_at_stdlibexample #158674 (library: Polish transmute'ssplit_at_stdlibexample)NonZero<char>in improper_ctypes #158680 (Avoid ICE forNonZero<char>in improper_ctypes)Hashderives from MIR types #158681 (Remove unnecessaryHashderives from MIR types)#[splat]#158684 (Add missing generic test coverage for#[splat])MacEager#158687 (StreamlineMacEager)r? @ghost
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