Sky130#35
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Covers RTL quality/bug analysis, test coverage, and ASIC/PDK readiness for the PULP HyperBus v2 controller. Concludes the design is sim/FPGA-ready but has no ASIC enablement (no synthesizable delay line, no SDC, no IO ring, tech cells unmapped) and no OpenRAM/PDK integration (openram/ is an empty venv). Assesses viability for SkyWater130, GF180, and TSMC 65nm. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Adds SkyWater130 ASIC enablement for the technology-dependent HyperBus PHY front-end (the AUDIT.md pulp-platform#1 blocker): - target/sky130/tech_cells_sky130.sv: synthesizable tc_clk_inverter/ tc_clk_gating/tc_clk_mux2 mapping to sky130_fd_sc_hd (real dlclkp ICG under SKY130_NATIVE_CELLS), removing the tech_cells_generic dependency. - target/sky130/configurable_delay.sky130.sv: synthesizable delay line from hard dlygate4sd3_1 cells + tap mux, replacing the sim-only #delay model and the absent proprietary generic_delay_* macro. - target/sky130/hyperbus_phy_sky130.sv: minimal self-contained PHY front-end top (clk gen, differential CK, 9x DDR out, RX delay). - syn/sky130/run.sh: Yosys synthesis to sky130_fd_sc_hd tt_025C_1v80. Minimal synthesis result: 107 cells, ~1249 um2, fully mapped (22 FFs, 9 DDR muxes, dlclkp ICG, 32 dlygate delay taps). Synthesis only; no P&R/ SDC/IO ring yet. See target/sky130/README.md for limitations and the sky130 speed reality (~10-25 MHz without a custom IO PHY). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
- openlane/hyperbus_phy_sky130/config.json: LibreLane (OpenLane 2) native flow config for the minimal PHY front-end. - syn/sky130/inspect.tcl: OpenROAD GUI script to view the placed netlist. - Documented the hardening result in target/sky130/README.md. Full RTL-to-GDS harden passes clean at 25 MHz (40 ns): 1184 instances, 5349 um2 std-cell area, 0 detailed-route/Magic DRC, LVS clean, setup/hold met (WNS +0.098/+0.423 ns). GDS/DEF/ODB emitted to runs/ (git-ignored). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Adds the full-controller ASIC flow on top of the minimal PHY harden: - syn/sky130/gen_full_rtl.sh: bender (resolve PULP deps) -> sv2v (SV->Verilog, --top prune to used hierarchy) -> single flat hyperbus_full.v. Bakes in the gotchas (zsh field-split, relative sv2v -I, VERILATOR/XSIM to strip SVA, SKY130_NATIVE_CELLS, and pinning the -1 'must-override' param defaults). - openlane/hyperbus/config.json: LibreLane config, top hyperbus_lint_wrap. - src/hyperbus_synth_wrap.sv: fix stale param IsClockODelayed -> UsePhyClkDivider (the wrapper would not elaborate before; AUDIT.md finding). - src/hyperbus_w2phy.sv: make two runtime-bound for-loops synthesis-portable (constant bound + runtime guard) so open tools (Yosys) accept them. Result: full AXI-128 + dual-PHY controller hardens clean at 25 MHz -- DRC (route/Magic/KLayout) 0, LVS clean, 0 setup/hold violations, ~1.25 mm2, 259k instances. Bring-up harden (slew/cap violations remain; no custom SDC). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
… CDC sv2v lowers cdc_2phase's `parameter type T` into scalar width params but sized the HyperBurstWidth-derived one as [0:0] (1 bit). Passing HyperBurstWidth=15 truncated it to 1, so the AXI<->PHY transaction CDC data ports resolved to 38 bits instead of 52 -- silently dropping the top 14 bits of tf_cdc_t (the write flag + burst[14:2]) on every crossing. The original SystemVerilog RTL is correct (tf_cdc_t is 52 bits on both sides); this was purely an sv2v artifact in the generated netlist. Fix: widen the extracted *HyperBurstWidth width params to [31:0] in gen_full_rtl.sh. Verified with Verilator -- the 38-vs-52 truncation is gone and the CDC data path is 52==52. NOTE: the previously-hardened GDS predates this fix and must be re-hardened for a functionally-correct macro. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
A pre-PnR STA sweep (worst corner ss_100C) shows 25 ns is the tightest period that still closes (WNS +0.29 ns); it goes negative below. 40 MHz. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Full hyperbus (AXI-128 + dual PHY) hardens clean at 40 MHz (25 ns) with the CDC width fix: DRC/LVS clean, 0 setup/hold violations, WNS +4.37 ns (layout headroom to ~48 MHz). Records the fmax sweep and the bring-up (non-signoff) caveats (slew/cap violations, no custom SDC). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
…mmands Adds to target/sky130/README.md: - external (RAM-facing) HyperBus pin table: 28 physical pins for NumPhys=2/NumChips=2, with direction and read/write behaviour, plus the internal SoC-facing (AXI/RegBus/clock) ports. - bandwidth: hyper_ck=clk_phy/2=20 MHz DDR -> 40 MT/s/DQ, 40 MB/s per PHY, 80 MB/s dual-PHY interleaved; up to 4 HyperRAM chips. - OpenROAD/KLayout commands to inspect the hardened layout. - reworked stale limitation pulp-platform#1 (full controller is now hardened). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
gen_full_rtl.sh now takes AXIW/NPHYS/OUT_NAME env vars (defaults 128/2, so the main build is unchanged) and patches a build-local wrapper copy so sv2v --top bakes the chosen AxiDataWidth/NumPhys. Adds openlane/hyperbus_small/ config for the AxiDataWidth=32, NumPhys=1 variant to demonstrate area scaling. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Small variant hardens clean at 40 MHz: 0.57 mm2 / 3781 flops / 14 pins vs the 128b/2-PHY 1.26 mm2 / 8186 flops / 28 pins -- ~2.2x smaller, not 10x, because a fixed ~20% AXI-protocol floor doesn't scale with data width. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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