Fix FuseSoC/XSIM issues

.github/workflows/lint.yml

@@ -31,3 +31,21 @@ jobs:
 
       - name: Run Verilator lint
         run: scripts/run_verilator.sh
+
+  # The FuseSoC core file duplicates the source list in Bender.yml and is only
+  # exercised by a single simulation target in CI, so a file added to one
+  # manifest but not the other goes unnoticed. Fail fast on such drift.
+  fusesoc-manifest:
+    name: FuseSoC core file sync
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v6
+
+      - name: Install Bender
+        uses: pulp-platform/pulp-actions/bender-install@v2
+        with:
+          version: 0.32.0
+
+      - name: Check FuseSoC core file against Bender manifest
+        run: scripts/check_fusesoc_manifest.sh

.gitlab-ci.yml

@@ -56,14 +56,13 @@ synopsys_dc:
 
 fuse_xsim:
   stage: build
-  allow_failure: true
   timeout: 5 minutes
   script:
     - bender checkout
     - mkdir fusesoc && cd fusesoc
     - uvx fusesoc library add axi ..
     - uvx fusesoc core list
-    - vitis-2022.1-zr uvx fusesoc run --tool xsim --target sim --no-export pulp-platform.org::axi:$(cat ../VERSION | sed s/-/./g)
+    - vitis-2025.2-dz uvx fusesoc run --tool xsim --target sim --no-export pulp-platform.org::axi:$(cat ../VERSION | sed s/-/./g)
 
 verilator_lint:
   stage: build

Bender.lock

@@ -1,6 +1,6 @@
 packages:
   common_cells:
-    revision: 03d98106aa19952a10360d2230def85144a0008b
+    revision: db42769334b4589b4b3fc671b34513bdb98be565
     version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
@@ -14,8 +14,8 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   tech_cells_generic:
-    revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845
-    version: 0.2.14
+    revision: 55cb54513e2d426be5992d311cb9d5dbcad10c78
+    version: null
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:

Bender.yml

@@ -24,9 +24,9 @@ remotes:
   pulp: https://github.com/pulp-platform
 
 dependencies:
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v2.0.0-beta.2 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: db42769334b4589b4b3fc671b34513bdb98be565 }
   common_verification: 0.2.5
-  tech_cells_generic: 0.2.14
+  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", rev: 55cb54513e2d426be5992d311cb9d5dbcad10c78 }
 
 export_include_dirs:
   - include

axi.core

@@ -15,6 +15,7 @@ filesets:
       # Level 0
       - src/axi_pkg.sv
       # Level 1
+      - src/axi_demux_id_counters.sv
       - src/axi_intf.sv
       # Level 2
       - src/axi_atop_filter.sv

scripts/check_fusesoc_manifest.sh

@@ -0,0 +1,49 @@
+#!/bin/bash
+# Copyright (c) 2026 ETH Zurich, University of Bologna
+#
+# Copyright and related rights are licensed under the Solderpad Hardware
+# License, Version 0.51 (the "License"); you may not use this file except in
+# compliance with the License.  You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Authors:
+# - Chen Wu <chenwu@iis.ee.ethz.ch>
+#
+# Check that the FuseSoC core file stays in sync with the Bender manifest.
+# Two invariants are enforced:
+#   1. Every source file Bender lists for this package (simulation and test
+#      targets) is referenced in the .core file.
+#   2. Every file referenced in the .core file exists on disk.
+
+set -euo pipefail
+cd "$(dirname "$0")/.."
+
+CORE_FILE=axi.core
+
+bender_files=$(bender script flist --relative-path --no-deps -t simulation -t test | sed '/^$/d' | sort -u)
+core_files=$(grep -oE '(src|test|include)/[A-Za-z0-9_./-]+\.svh?' "$CORE_FILE" | sort -u)
+
+ret=0
+
+missing_in_core=$(comm -23 <(echo "$bender_files") <(echo "$core_files"))
+if [ -n "$missing_in_core" ]; then
+    echo "ERROR: listed in Bender.yml but missing from $CORE_FILE:" >&2
+    echo "$missing_in_core" >&2
+    ret=1
+fi
+
+for f in $core_files; do
+    if [ ! -f "$f" ]; then
+        echo "ERROR: listed in $CORE_FILE but does not exist: $f" >&2
+        ret=1
+    fi
+done
+
+if [ "$ret" -eq 0 ]; then
+    echo "$CORE_FILE is in sync with Bender.yml"
+fi
+exit "$ret"

src/axi_test.sv

@@ -1298,9 +1298,9 @@ package axi_test;
     task run(input int n_reads, input int n_writes);
       automatic logic  ar_done = 1'b0,
                        aw_done = 1'b0;
+      // Cache-Partition: randomize the patid
+      automatic user_t ax_user = rand_user(AX_USER_RANGE, AX_USER_RAND);
       fork
-        // Cache-Partition: randomize the patid
-        automatic user_t ax_user = rand_user(AX_USER_RANGE, AX_USER_RAND);
         begin
           send_ars(n_reads, ax_user);
           ar_done = 1'b1;

test/tb_axi_isolate.sv

@@ -202,6 +202,7 @@ module tb_axi_isolate #(
   end
 
 
+`ifndef XILINX_SIMULATOR
   default disable iff (!rst_n);
   aw_unstable: assert property (@(posedge clk)
       (slave.aw_valid && !slave.aw_ready) |=> $stable(slave.aw_addr)) else
@@ -218,6 +219,7 @@ module tb_axi_isolate #(
   r_unstable:  assert property (@(posedge clk)
       (master.r_valid && !master.r_ready) |=> $stable(master.r_data)) else
       $fatal(1, "R is unstable.");
+`endif
 
 
 endmodule

test/tb_axi_lite_regs.sv

@@ -300,6 +300,7 @@ module tb_axi_lite_regs #(
   endtask : check_q
 
   // Some assertions for additional checking.
+`ifndef XILINX_SIMULATOR
   default disable iff (~rst_n);
   for (genvar i = 0; i < TbRegNumBytes; i++) begin : gen_check_ro_bytes
     if (TbAxiReadOnly[i]) begin : gen_check_ro
@@ -320,6 +321,7 @@ module tb_axi_lite_regs #(
         (!reg_load[i] && !wr_active[i]) |=> $stable(reg_q[i])) else
         $fatal(1, "Byte %0d is unstable, when no AXI write or direct load.", i);
   end
+`endif
 
   initial begin : proc_stop_sim
     wait (end_of_sim);

test/tb_axi_lite_to_apb.sv

@@ -169,6 +169,7 @@ module tb_axi_lite_to_apb #(
 
   // pragma translate_off
   `ifndef VERILATOR
+  `ifndef XILINX_SIMULATOR
   // Assertions to determine correct APB protocol sequencing
   default disable iff (!rst_n);
   for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_assertions
@@ -211,6 +212,7 @@ module tb_axi_lite_to_apb #(
         ((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pstrb)));
   end
   `endif
+  `endif
   // pragma translate_on
 
   //-----------------------------------

test/tb_axi_modify_address.sv

@@ -209,6 +209,7 @@ module tb_axi_modify_address #(
   `AXI_ASSIGN_TO_R(r_act, upstream)
 
   // Assert that actual responses match expected responses.
+`ifndef XILINX_SIMULATOR
   default disable iff (~rst_n);
   aw: assert property(@(posedge clk)
     downstream.aw_valid |-> aw_act == aw_exp
@@ -225,5 +226,6 @@ module tb_axi_modify_address #(
   r: assert property(@(posedge clk)
     upstream.r_valid |-> r_act == r_exp
   ) else $error("R %p != %p!", r_act, r_exp);
+`endif
 
 endmodule