🐛 [valu/vmfpu] Reduction deadlock & FP-compare fixes (#447, #451)#470
Open
saurav-fermions wants to merge 5 commits into
Open
🐛 [valu/vmfpu] Reduction deadlock & FP-compare fixes (#447, #451)#470saurav-fermions wants to merge 5 commits into
saurav-fermions wants to merge 5 commits into
Conversation
A reduction whose init state is entered while the VALU result queue still holds valid entries deadlocks the lane: the reduction datapath and the result queue contend for the same sequential state and neither makes progress. This reproduces with vredsum following a widening op that leaves results queued. Gate the reduction-init transition on result_queue_cnt_d == '0 so a new reduction only starts once previous results have drained. Refs pulp-platform#451
Self-contained reproducer for the reduction deadlock (pulp-platform#451): a widening op (vwaddu.wv) that leaves results in the VALU result queue followed by vredsum.vs. Verified on the Verilated model (4 lanes, VLEN=4096): * with the valu.sv fix: PASS (reduction result = 384, ~0xb9c cycles) * without the fix: hangs (testbench timeout) -- deadlock reproduced Refs pulp-platform#451
Floating-point comparisons (vmfeq/vmfne/vmflt/vmfle/vmfgt/vmfge) are non-computational CVFPU operations, in the same family as vfmin/vfmax/vfsgnj* which already map to LatFNonComp. They were missing from the latency function and fell through to the arithmetic, sew-based default latency. The wrong latency mis-aligns the mask-routing tag that travels alongside the result, so under pipeline pressure a comparison result is written to the VRF instead of being routed to the mask unit. Map [VMFEQ:VMFGE] to LatFNonComp. The enum range is contiguous and isolated (FP reductions before, integer comparisons after). NOTE: this is a pipeline-timing change and must be confirmed against the FP-compare regression suite in simulation before merging upstream. Refs pulp-platform#447
Self-checking reproducer for the FP-compare mask-routing desync (pulp-platform#447): long-latency FP ops (vfdiv + vfmacc) kept in flight across a vmfge that produces v0, then a masked vfadd consuming v0.t. Verified on the Verilated model (4 lanes, VLEN=4096): * with the vmfpu.sv fix: PASS (mask {0,0,1,1} applied -> {100,100,12,16}) * without the fix: FAIL (mask mis-routed; op runs unmasked -> {4,8,12,16}) Refs pulp-platform#447
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Two lane execution-unit correctness fixes, each atomic and accompanied by a
Spike-vs-Ara differential reproducer.
valu) — Start integer reductions only when the VALU result queue is empty, fixing avredsumdeadlock.vmfpu) — Use the non-computational FPU latency for floating-point comparisons, fixing a mask-routing desync.Verification
Reproducers
vredsum_deadlockandvmfeq_routeare checked against the Spikegolden model and pass on the Verilated Ara model at 2/4/8/16 lanes.
Checklist
Fixes #447
Fixes #451
Developed with SAIGE, Fermions' autonomous RTL/EDA debugging agent; root-caused, tested, and signed off by the submitter (@saurav-fermions).