Feat/zvbb bitmanip#465
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Introduce the configuration mechanism for the RISC-V vector crypto
extensions ahead of the actual instruction implementations. This adds
the crypto_support_e enumeration to ara_pkg and threads a CryptoSupport
parameter (defaulting to CryptoSupportNone) through the full module
hierarchy: ara_soc -> ara_system -> ara -> {ara_dispatcher, lane ->
vector_fus_stage -> valu -> simd_alu}.
No instructions are implemented yet; subsequent commits enable specific
extensions by adding enum values, helper predicates, and datapath logic
gated on this parameter.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add the Zvkb (Vector Cryptography Bit-manipulation) extension, gated behind the CryptoSupportBitmanip configuration. Implements the following instructions in the SIMD ALU, with dispatch for .vv, .vx, and .vi encodings: - vandn.vv/vx: bitwise AND-with-complement - vrol.vv/vx, vror.vv/vx/vi: element-wise rotate left/right - vbrev8.v: bit-reverse within each byte - vrev8.v: byte-reverse within each element (endian swap) Adds a Zvkb() predicate over crypto_support_e, the new ALU op enums, and a riscv-tests suite (zvkb.c) covering all instructions across e8/e16/e32/e64 with masked variants. Enables zvkb in the LLVM and spike ISA strings. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add the Zvbb (Vector Basic Bit-manipulation) extension on top of Zvkb, gated behind the CryptoSupportBasicBit configuration. Since Zvbb implies Zvkb, the Zvkb() predicate is widened to also match Zvbb. Adds: - vbrev.v: full bit-reverse within each element - vclz.v / vctz.v: count leading / trailing zeros - vcpop.v: population count per element - vwsll.vv/vx/vi: widening shift-left-logical, with per-operand LMUL alignment checks Adds the supporting SIMD ALU helper functions and a riscv-tests suite (zvbb.c) covering all instructions with masking variants. Switches the toolchain and spike ISA strings from zvkb to zvbb (which subsumes it). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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Add initial scaffold for RISC-V Vector Crypto instructions, add zvkb and zvbb extension support.