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1. rv32i_uvm rv32i_uvm Public

   A pipelined RV32I RISC-V CPU built in SystemVerilog and verified with UVM, SVA, and Spike differential testing.

   SystemVerilog

2. fpga-ipod fpga-ipod Public

   Flash-streamed audio playback on DE1-SoC with PS/2 keyboard control and a PicoBlaze-driven LED audio-strength meter

   Verilog

3. simt-matrix-multiply-accel simt-matrix-multiply-accel Public

   SIMT-style GPU in SystemVerilog for DE1-SoC (Cyclone V)

   SystemVerilog

4. nios-dds-cdc nios-dds-cdc Public

   Custom Nios II Avalon peripherals: DDS waveform generator, LFSR interrupt source, and clock-domain-crossing synchronizers

   SystemVerilog

5. UBC-ORCA/riscv-debug-tutorial UBC-ORCA/riscv-debug-tutorial Public

   An end-to-end tutorial explaining how RISC-V run-control debug works: how GDB, OpenOCD, the Debug Transport Module, and the Debug Module fit together with a CV32E20 soft core, plus a section on wha…

   SystemVerilog 1

6. rc4-deciphering-circuit rc4-deciphering-circuit Public

   Parallel hardware key-recovery attack on RC4, implemented in SystemVerilog on a DE1-SoC FPGA

   Verilog