Qwen3.5-4B Q4_K_M: F2 guard rejects the CUDA path on GB10 at the first decode position (cosine 0.8675); 0.70.3 too, sm_89 passes #4958

Refs #3719

What fails

On a GB10 (sm_121), the F2 CPU-parity guard rejects the CUDA path for Qwen3.5-4B Q4_K_M at position 64. That is the first decode step after the 64-position batched prefill. The serve then falls back to CPU, so apr code on this model and host runs on CPU.

Backend: GPU (CUDA, NVIDIA GB10, 122502 MB VRAM) [qwen35 hybrid forward, #3090]
F2 guard: validating on this run (no receipt for this model) [source=fresh]
warning: GPU output diverges from CPU at position 64 (argmax 74455 != 74455, cosine 0.8675); min cosine 0.8675, validated via batched prefill — falling back to CPU
warning: GPU (CUDA) qwen35 path rejected, falling back to CPU: the F2 CPU-parity guard rejected the GPU path

Cosine 0.8675 is below F2_CATASTROPHIC_COSINE (0.90), so the guard is right to refuse.

It is not a regression since 0.70.3

• The model file is the same on both hosts: sha256 00fe7986ff5f6b463e62455821146049db6f9313603938a70800d1fb69ef11a4.
• The prompt is the same on every row. It is the exact apr code request (fixture system prompt with APR_CONFIG set to an empty dir), and the driver binary is the same.
• The swap row changed only the serve child. It is the released 0.70.3 binary, and the GPU line above is its own stderr.
• F2 runs fresh every time: each run uses an empty APR_F2_RECEIPT_DIR.
• The failure is deterministic: three runs gave the same position and the same cosine to four digits.
• It depends on the prompt. A shorter, hand-built prompt passes F2 on the same GB10 and model, so this repro needs the full apr code prompt.

A second, smaller defect: the message

f2_divergence_msg (crates/aprender-serve/src/infer/inference_result.rs) always prints argmax {gpu} != {cpu}. Here both are 74455. The rejection is on cosine alone, but the line reads as an argmax mismatch. When the two match, it should say so, for example argmax 74455 (agrees), cosine 0.8675 < 0.90, and name the floor that fired.

Repro

The harness is on branch fix/3719-apr-code-qwen35-cuda-071. That branch is not yet in a PR, because it waits for a slot.

APR_BIN_REQUIRE=head APR_BIN=<CUDA build> scripts/apr_code_edit_verify.sh \
  --model Qwen3.5-4B-Q4_K_M.gguf --host <name> --out <fresh dir> --gpu-q 1

Read <out>/serve-child.stderr for the F2 lines.

What this blocks

This is the only FAIL cell of #3719 (Qwen3.5 4B/9B × lambda/gx10). The other three cells pass on CUDA.

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