Qwen3.5 batched prefill has no f32 dequant for IQ2_XXS, IQ3_S, IQ3_XXS, Q2_K: apr run --gpu exits 14 on Qwen3.5-0.8B-UD-IQ2_XXS #4952

Sub-ticket of #3953. apr run --gpu on Qwen3.5-0.8B-UD-IQ2_XXS.gguf exits 14 at main 9259972. It fails closed: generation falls back to the CPU, and --gpu refuses to call that a success.

Cause

• The Qwen3.5 batched prefill dequantizes every projection weight to f32 (qwen35_dequant_f32, crates/aprender-serve/src/cuda/executor/gdn_prefill_ops.rs) before its GEMM.
• It does this in every APR_QWEN35_PREFILL_GEMM mode. The f16 mode caches an f16 copy of each weight, but it builds that copy from the same f32 dequant.
• APR_QWEN35_SESSION_PREFILL=per-token does not avoid it either, because the parity probe always runs the batched prefill.
• qwen35_dequant_f32 has device kernels for Q4_K, Q5_K, Q6_K, Q8_0, F16 and IQ4_XS. Any other type returns InvalidParameter("no f32 dequant kernel").
• The IQ2_S (ggml 22) has no CUDA GEMV — 0.69.1 release blocker #3953 branch adds IQ2_S, bit-exact on the device (see below).

This model holds five types with no prefill dequant. The decode GEMVs for all five are on main. #3953's "four types" counted the missing GEMVs; IQ3_S already had a GEMV but has no dequant.

Rows

• IQ2_XXS -> f32 dequant
• IQ3_S -> f32 dequant
• IQ3_XXS -> f32 dequant
• Q2_K -> f32 dequant
• apr run --gpu rc 0 on the model, with the parity probe passing, on sm_89 (RTX 4090)

Acceptance (each row)

The IQ2_S dequant on the #3953 branch passed each of these:

• Bit-exact (to_bits) against the CPU oracle on every real tensor of the type in the model.
• Bit-exact on synthetic shapes, including a row whose last block is partial. The scratch is pre-filled with NaN and checked for out-of-bounds writes.
• Planted faults in the PTX (signs, high bits, scale selector, d, row stride, tail guard) each turn a test RED. The restored tree is green.
• The PTX is ASCII-only, assembles under ptxas, and is loop-free. A loop-free kernel is never touched by the apr-cli: gate realizar/CUDA imports behind feature flags for aarch64 builds #480 sm_121 backward-branch pass (P0: IQ3_S/IQ2_S GEMV kernels fail to load on cc>=12 (GB10/Blackwell) — GH-480 PTX patch injects .reg inside a global array initializer #4096).

Decided by a planted quorum round (3 of 3 counted lanes, degraded: same-family): the IQ2_S dequant lands alone under #3953, and the other four go here, started at once, not deferred.

Owner: aprender-wprodmodels.