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Q5_K and Q6_K have no AVX-512 kernel at all, so an AVX-512 host runs its largest tensor on 256-bit lanes #2605

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Description

@noahgift

Severity: P1 — found by the pre-release multi-platform dogfood sweep (intel/AVX-512 lane).

Measured against the published apr 0.63.0 from crates.io on the Intel receipt host
(Xeon W-3245, 16C/32T, AVX-512F/BW/CD/DQ/VL/VNNI), not a local build.

Where

crates/aprender-serve/src/quantize/fused_q5k_q6k.rs — fused_q6k_dot has only _avx2 and _simd variants; no AVX-512 sibling exists anywhere in the workspace

Defect

Q5_K and Q6_K have NO AVX-512 kernel at all, so even if F1 were fixed the AVX-512 host would still run its single largest tensor on 256-bit lanes. ISA coverage in the shipped binary is lopsided: 40 avx2 symbols vs 4 avx512 (of which 2 are the VNNI kernels proven dead in F1, plus fused_q4_0_q8_0_dot_avx512_vnni which also never fired). AVX-512 was implemented only for the Q4_K x Q8_K and Q4_0 x Q8_0 dots. This matters concretely on Q4_K_M: output.weight (the lm_head) is Q6_K [1536, 151936] at 182.6 MB — the largest single tensor in the file — and 29 of 339 tensors are Q6_K.

Reproduction

MEASURED on mac-server, published binary:
  nm /home/noah/.cargo/bin/apr | grep -E ' [tT] ' | grep -c '8realizar8quantize.*avx512vnni'  -> 2
  nm … | grep -c '8realizar8quantize.*avx512'                                                  -> 4
  nm … | grep -c '8realizar8quantize.*avx2'                                                    -> 40
  nm … | grep -c '8realizar8quantize.*scalar'                                                  -> 1
  nm … | grep -oE 'fused_q6k_dot[a-z0-9_]*'  ->  fused_q6k_dot, fused_q6k_dot_avx2, fused_q6k_dot_simd   (no avx512)
  grep -rn 'fn ggml_style' --include='*.rs' crates/  -> exactly 2, both _avx2 (q4k_dot_ggml_style.rs:38,63); no AVX-512 sibling
Runtime, same 8-token generation: fused_q6k_dot_avx2 = 8,320,128 calls (identical on Zen 4).
Tensor mix from `apr tensors` on the 1.5B Q4_K_M: 170 Q4_K, 141 F32, 29 Q6_K, largest = output.weight [1536,151936] Q6_K 182.6 MB.

Filed from the 0.64.0 pre-release sweep. Scope AVX512-SPECIFIC.

Activity

  1. added
    pp-067PP-066 spec §6: 0.67 lane (carried row)
    on Sep 5, 2026
  2. noahgift commented on Sep 5, 2026

    @noahgift
    MemberAuthor

    0.67 lane — attaches to PP-066 spec §6 row W-B kernel.

    No AVX-512 Q5_K/Q6_K kernel exists (lm_head Q6_K runs on 256-bit lanes). Kernel work is 0.67 (D-1); nearest §6 row W-B kernel; CPU-x86 gap flagged.

    Instance of class #2880 — the shipped CPU path runs a narrower ISA or algorithm than the host supports.

    PP-066 triage 2026-09-05 (issue #2873); ledger docs/audits/pp-066-triage-2026-09-05.md.

  3. modified the milestones: 0.68.0, 0.70.0, 0.73.0, 0.73.0 on Sep 10, 2026
  4. noahgift commented on Sep 23, 2026

    @noahgift
    MemberAuthor

    triage 2026-09-23 (aprender-dd, standing triage owner): milestoned to 0.73.0, theme llama.cpp Parity (performance, kernels, parity benches); it moved out of backlog (the 2026-09-17 overflow bucket, not a release).

  5. noahgift commented on Sep 24, 2026

    @noahgift
    MemberAuthor

    Closed by paiml-implement — folded into epic #3999 (triage evidence/triage-1717.md)

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