Fix clock and reset names in controller bind - #1072
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cv32e40p_controller has ports clk and rst_n, not clk_i and rst_ni. The bind used clk_i and rst_ni, which do not exist there, so the tool creates new signals that nothing drives. The controller assertions then have no working clock. Connect clk and rst_n, the same as the ID and EX stage binds already do. Signed-off-by: Avinash Kollu <avinashkollu123@gmail.com>
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Problem
In
scripts/formal/src/cv32e40p_bind.sv, the controller assertions are connected toclk_iandrst_ni. The controllerdoes not have these signals. Its ports are
clkandrst_n. So the tool creates new signals that nothing drives, and thecontroller assertions have no working clock.
Verilator lint shows it:
Signal definition not found, creating implicitly: 'clk_i'(suggested alternative:clk), and thesame for
rst_ni.Fix
Connect
clkandrst_n, the same as the ID and EX stage binds already do. Two lines. After the change the lint warnings are gone.Please note
I do not have Questa, so I could not rerun the existing controller assertions. It would be good to rerun them after this change.