[PW_SID:1142016] Add Counter delegation ISA extension support - #2431
[PW_SID:1142016] Add Counter delegation ISA extension support#2431linux-riscv-bot wants to merge 21 commits into
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Sashiko pointed out various UAF and memory leak issues around pmu_sbi_device_probe() error paths. If the probe fails, here are list of cleanups needed. a. Already registered pmu must be freed b. per cpu IRQ must be released c. pmu_ctr_list data structure must be freed d. cpu hotplug state must be cleaned up only if added. Fix the resource cleanup by reorganizing the code around probe failure. Reported-by: Sashiko AI <sashiko-bot@kernel.org> Link: https://patch.msgid.link/20260701-counter_delegation-v8-1-7909f863a645@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Atish Patra <atishp@meta.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This adds definitions of new CSRs and bits defined in the Smcsrind and Sscsrind ISA extensions. These CSRs enable the indirect CSR accesses mechanism to access any indirect CSRs in M-, S-, and VS-mode. The range of the select values and ireg will be defined by the ISA extension that are based on the Smcsrind and Sscsrind extensions. Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-2-7909f863a645@meta.com [pjw@kernel.org: clean up the patch description; use official RISC-V extension names] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The S[m|s]csrind extensions extend the indirect CSR access mechanism defined in Smaia/Ssaia extensions. This patch just enables the definition and parsing. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-3-7909f863a645@meta.com [pjw@kernel.org: use official RISC-V extension names in the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the S[m|s]csrind ISA extension description. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-4-7909f863a645@meta.com [pjw@kernel.org: use official extension names in the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The indirect CSR requires multiple instructions to read/write CSR. Add a few helper macros for ease of usage. These have to be macros rather than functions. csr_read()/csr_write() stringify their CSR argument into the inline asm template via __ASM_STR(), so the CSR number must be a literal token; passing it as a function parameter emits "csrr %0, iregcsr", which the assembler rejects with "unknown CSR `iregcsr'". The stringification happens in the preprocessor, before inlining or constant propagation, so it cannot be worked around by forcing inlining or by only ever passing constants - gcc 12, gcc 16 and clang 22 all reject it alike. Underneath, csrr/csrw encode the CSR as a 12-bit immediate and RISC-V has no register-indirect form, which is also why asm/csr.h keeps every one of its accessors as a macro. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-5-7909f863a645@meta.com [pjw@kernel.org: expand "ind" abbreviation] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Smcntrpmf extension allows M-mode to enable privilege mode filtering for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are available in Ssccfg only if Smcntrpmf is present. That's why, kernel needs to detect presence of Smcntrpmf extension and enable privilege mode filtering for cycle/instret counters. Reviewed-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-6-7909f863a645@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the description for Smcntrpmf ISA extension Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-7-7909f863a645@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This adds the scountinhibit CSR definition and S-mode accessible hpmevent bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop counters directly from S-mode without invoking SBI calls to M-mode. It is also used to figure out the counters delegated to S-mode by the M-mode as well. Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-8-7909f863a645@meta.com [pjw@kernel.org: fixed subject typo] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Smcdeleg extension allows the M-mode to delegate selected counters to S-mode so that it can access those counters and correpsonding hpmevent CSRs without M-mode. Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters and new supervisor-level state. This patch just enables these definitions and enable parsing. Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-9-7909f863a645@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add description for the Smcdeleg/Ssccfg extension. Signed-off-by: Atish Patra <atishp@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260701-counter_delegation-v8-10-7909f863a645@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
With Ssccfg/Smcdeleg, supervisor mode can program and access the hpmcounters and events directly, without the SBI PMU extension. The SBI PMU extension is still required for firmware counters. Restructure the existing SBI PMU code so the hpmcounter/event helpers can be shared between the SBI and the counter delegation paths that follow. The driver, file, module and Kconfig names are intentionally kept unchanged to avoid backport churn and userspace breakage (module listings, udev rules, cmdline options). No functional change intended. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
If both counter delegation and SBI PMU is present, the counter delegation will be used for hardware pmu counters while the SBI PMU will be used for firmware counters. Thus, the driver has to probe the counters info via SBI PMU to distinguish the firmware counters. The hybrid scheme also requires improvements of the informational logging messages to indicate the user about underlying interface used for each use case. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
There are few new RISC-V ISA exensions (ssccfg, sscsrind, smcntrpmf) which allows the hpmcounter/hpmevents to be programmed directly from S-mode. The implementation detects the ISA extension at runtime and uses them if available instead of SBI PMU extension. SBI PMU extension will still be used for firmware counters if the user requests it. The current linux driver relies on event encoding defined by SBI PMU specification for standard perf events. However, there are no standard event encoding available in the ISA. In the future, we may want to decouple the counter delegation and SBI PMU completely. In that case, counter delegation supported platforms must rely on the event encoding defined in the perf json file or in the pmu driver. For firmware events, it will continue to use the SBI PMU encoding as one can not support firmware event without SBI PMU. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
When the PMU SBI extension is not implemented, sbi_v2_available should not be set to true. The SBI implementation for counter config matching and firmware counter read should also be skipped when the SBI extension is not implemented. Signed-off-by: Atish Patra <atishp@meta.com> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The counter restriction specified in the json file is passed to the drivers via config2 paarameter in perf attributes. This allows any platform vendor to define their custom mapping between event and hpmcounters without any rules defined in the ISA. For legacy events, the platform vendor may define the mapping in the driver in the vendor event table. The fixed cycle and instruction counters are fixed (0 and 2 respectively) by the ISA and maps to the legacy events. The platform vendor must specify this in the driver if intended to be used while profiling. Otherwise, they can just specify the alternate hpmcounters that may monitor and/or sample the cycle/instruction counts. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Qemu is identified by its marchid. Older Qemu reports all-zero mvendorid/marchid/mimpid, while newer Qemu reports the marchid 0x2a (42) allocated to it in the RISC-V ISA manual [1]. Register the events for both ids so they are available across Qemu versions. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
RISC-V relies on the event encoding from the json file. That includes arch standard events. If event code is present, event is already updated with correct encoding. No need to update it again which results in losing the event encoding. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Counter delegation lets supervisor mode choose the hpmcounter for an event, but the hardware may only allow a given event on a subset of counters. Add a RISC-V specific "CounterIDMask" json event field, handled like the other arch-specific entries in event_fields[], that carries the allowed-counter bitmask through to the driver's existing counterid_mask (config2:0-31) format. The value is the bitmask directly so no counter-list to bitmask conversion is needed, and because the field is RISC-V specific it is a no-op for every other architecture's events (unlike the shared "Counter" field). Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 1: "[v9,01/20] RISC-V: perf: fix resource cleanup on driver probe failure" |
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Patch 18: "[v9,18/20] RISC-V: perf: Add Qemu virt machine events" |
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Patch 18: "[v9,18/20] RISC-V: perf: Add Qemu virt machine events" |
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Patch 18: "[v9,18/20] RISC-V: perf: Add Qemu virt machine events" |
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Patch 18: "[v9,18/20] RISC-V: perf: Add Qemu virt machine events" |
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Patch 18: "[v9,18/20] RISC-V: perf: Add Qemu virt machine events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 19: "[v9,19/20] tools/perf: Support event code for arch standard events" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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Patch 20: "[v9,20/20] tools/perf: Add RISC-V CounterIDMask event field" |
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PR for series 1142016 applied to workflow__riscv__fixes
Name: Add Counter delegation ISA extension support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1142016
Version: 9