[PW_SID:1141484] Initial device tree support for StarFive JHB100 SoC - #2423
[PW_SID:1141484] Initial device tree support for StarFive JHB100 SoC#2423linux-riscv-bot wants to merge 6 commits into
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Add new compatible string for Dubhe-70. Dubhe-70 is a low power RISC-V cpu core from StarFive Technology. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add compatible string for StarFive JHB100 plic. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add device tree bindings for the StarFive JHB100 RISC-V SoC. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…tible Add "starfive,jhb100-uart" compatible string, with "snps,dw-apb-uart" as the fallback. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC, PMU, UART, INTC and 1GB DDR. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 1: "[v3,1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles" |
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Patch 2: "[v3,2/5] dt-bindings: interrupt-controller: Add StarFive JHB100 plic" |
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PR for series 1141484 applied to workflow__riscv__fixes
Name: Initial device tree support for StarFive JHB100 SoC
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1141484
Version: 3