(WIP) perf(comm): add two-stage producer-direct reduction - #1141
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Use a reduce-scatter/all-gather Iris path for larger symmetric outputs while retaining the one-stage path for small payloads. Signed-off-by: Sanket Pandit <sanket.pandit@amd.com>
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@panditsa I am validating the #1132 M=8 path on current main ( Exact 131072/1024 TP8/EP8 forced-acceptance=1 now measures 36.80 ms/round versus 17.06 ms ordinary decode ( Unless you prefer a different arrangement, I plan to benchmark these existing changes independently on current main: #1141, the M=8 |
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Exact #1132 result on The same #1141 code inside #1141 + #1142 + #1146 does register and completes; that full stack improves forced 131K/1K TPOT from 36.80 to 36.25 ms (-1.49%, three runs). This suggests the downstream state/orchestration changes are required for an E2E-valid use of the two-stage path. |
These optimizations help with 4K/1K scenarios but I have not been using/looking at dspark and 131072/1024 performance. Feel free to continue with your investigations. I am glad these PRs are at least getting us to serving state :) |
Summary
Performance
Exact parent
2ebd8f81→ head60babeb9, world-size 8 BF16 producer-direct reduction under CUDA-graph replay, critical-rank p50:M=2/4 remain on the one-stage path; M=8/16 cross the world-size-8 BF16 two-stage threshold.
Tests
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