[LLVMCPU] vlen attribute for DataTiledMMAAttr for RISCV + FP16 port - #24858
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[LLVMCPU] vlen attribute for DataTiledMMAAttr for RISCV + FP16 port#24858egebeysel wants to merge 3 commits into
vlen attribute for DataTiledMMAAttr for RISCV + FP16 port#24858egebeysel wants to merge 3 commits into
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`getIntrinsicMNKShape` states how many M/N/K elements one invocation of an intrinsic computes, independent of how those elements are laid out in registers. Selection scores candidates on this shape and the sibling-pairing validator checks M and N against it, so every intrinsic declares one, including scalable ones, which declare their base sizes. A scalable and a non-scalable intrinsic should never compete for the same matmul, so comparisons stay like-for-like. The hand-rolled swizzles for intrinsics whose tiles are not row-major move into `getNonRowMajorIntrinsicSwizzle`. Signed-off-by: Ege Beysel <beyselege@gmail.com>
For RISC-V, the vector length per SIMD register is not fixed and is configurable. Therefore, the tile shape of an intrinsic and the total SIMD register bit budget is also parameterized by the vector length. In order for all of these vector length configurations to share a single intrinsic and not duplicate it per-configurable-vlen, we add a `vlen` parameter to the `DataTiledMMAAttr`, which in combination with the intrinsic itself gives the exact shape information, as well as the register budget. These are derived from the `+zvl*b` flags. Signed-off-by: Ege Beysel <beyselege@gmail.com>
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Materializes data-tiled f16 matmul encodings to `iree_codegen.inner_tiled` on RISC-V V targets with Zvfh, as the first consumer of the `vlen` attribute parameter. One enum pair covers every vector length. `MMA_RISCV_V_VFMACC_1x8VLsx1_F16_F16` and its M<->N-swapped sibling describe a 1x8VLsx1 tile where `8VLs` describes 8 * vscale, and `s` stands for static. This results in one vfmacc.vf instruction with LMUL=2 register group at 16-bit elements, matching mmt4d. Lowering to LLVM intrinsics is not included. Signed-off-by: Ege Beysel <beyselege@gmail.com>
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For RISC-V, the vector length per SIMD register is not fixed and is configurable. Therefore, the tile shape of an intrinsic and the total SIMD register bit budget is also parameterized by the vector length. In order for all of these vector length configurations to share a single intrinsic and not duplicate it per-configurable-vlen, we add a
vlenparameter to theDataTiledMMAAttr, which in combination with the intrinsic itself gives the exact shape information, as well as the register budget. These are derived from the+zvl*bflags.Furthermore, add materialization for data-tiled f16 matmul encodings to
iree_codegen.inner_tiledon RISC-V V targets with Zvfh, as the first consumer of thevlenattribute parameter. Lowering to LLVM intrinsics is not included.Towards #24311
Assisted-by: Claude Code