[CI] Add bare-metal RISCV 64 sample and QEMU smoke test - #24844
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[CI] Add bare-metal RISCV 64 sample and QEMU smoke test#24844phemashekar wants to merge 3 commits into
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The HAL_Loader and HAL_Inline dialects registered no DialectInlinerInterface, so CombineInitializers could not inline any util.initializer containing their ops into the combined initializer: - hal_loader: the multi-block executable-loading initializer broke all inline-dynamic compilation. - hal_inline: the buffer-allocating initializer of mutable globals broke stateful programs under both inline-dynamic and inline-static. Both dialects now register the same permissive inliner interface used by the HAL dialect. The hal_loader dispatch runtime shim used sizeof(iree_vm_abi_rIiii_t) (which may include trailing struct padding) as the offset of the variadic segment, but the VM writes that segment immediately after the last fixed field with no trailing padding; every dispatch failed with an argument/result signature mismatch. The shim now sizes the fixed prefix through its final field. Assisted-by: Claude Code Signed-off-by: Pooja Hemashekar <hemashekar@roofline.ai>
iree_vm_buffer_destroy assumed every non-module-owned buffer was co-allocated with its data by iree_vm_buffer_create, and therefore freed the handle with iree_allocator_free_aligned. This is invalid for buffers initialized in-place over caller-owned storage, such as the inline HAL storage buffer wrapper, and caused the wrapper to leak in the inline execution model end-to-end test. Hence, tag buffers created/cloned with IREE_VM_BUFFER_ACCESS_COALLOCATED and only use the aligned free path for those. Other buffers pass the handle directly to their allocator. Also initialize the inline storage buffer's host_allocator and hal_buffer fields. Without this, destroying the wrapper would use a null allocator and fail to release the retained HAL buffer. Assisted-by: Claude Code Signed-off-by: Pooja Hemashekar <hemashekar@roofline.ai>
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Adds samples/baremetal_riscv64: a single-op inference runner for bare-metal riscv64 (IREE_PLATFORM_GENERIC, inline HAL) executed on qemu-system-riscv64 (-machine virt, no OS, semihosted I/O), and a pkgci job that builds it and runs it for both the llvm-cpu (inline-dynamic, embedded-ELF loader) and vmvx-inline (inline-static) backends. Design notes: - samples/simple_embedding's CMake pattern (iree_cc_binary + iree_bytecode_module) is the model for the sample, but not its full-HAL runtime code: iree_hal_sync_device_create is currently unusable on IREE_PLATFORM_GENERIC (device creation eagerly acquires a proactor and no generic proactor implementation exists), so the runner uses the inline HAL (hal_inline + hal_loader) instead. - One toolchain/sysroot end to end: xPack riscv-none-elf-gcc, whose newlib is built -mcmodel=medany (QEMU virt RAM starts at 0x80000000, outside medlow range) and ships semihost.specs. The riscv-collab LLVM toolchain was rejected because its newlib is medlow-built, which would have forced linking against a second toolchain's newlib -- not a stable ABI boundary. - The sample is added with EXCLUDE_FROM_ALL and guarded on a GNU toolchain: its link options rely on GCC spec files, so it must not enter the default all build of other Generic riscv64 configurations (e.g. generic_riscv64.cmake with clang). CI builds it explicitly via --target samples/baremetal_riscv64/all. - The toolchain download is pinned by sha256. - Four ctype-macro call sites (string_view.c, regex lexer.c) now cast to unsigned char: newlib's ctype macros index a table with the argument and GCC's -Werror=char-subscripts rejects plain char there. Assisted-by: Claude Code Signed-off-by: Pooja Hemashekar <hemashekar@roofline.ai>
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Please review only the last commit in this PR since this is based off of #24827 |
phemashekar
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August 25, 2026 16:36
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August 25, 2026 16:36
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Adds
samples/baremetal_riscv64, a single-op inference runner for bare-metal RISCV 64 underqemu-system-riscv64(-machine virt, no OS, semihosted I/O), together with a pkgci smoke test.The sample covers two execution paths:
llvm-cpuusinginline-dynamicand the embedded-ELF loader.vmvx-inlineusinginline-static.The runner uses the inline HAL instead of the full-HAL implementation following
samples/simple_embedding, because HAL device creation currently requires a proactor thatIREE_PLATFORM_GENERICdoes not provide.The runtime is compiled and linked using an xPack GCC/newlib sysroot. Its newlib is built with
-mcmodel=medanyrequired for QEMUs RAM base and providessemihost.specsfor semihosted I/O and exit handling.No HAL device drivers are enabled; the embedded-ELF loader is enabled explicitly for the LLVMCPU runner. The sample is
EXCLUDE_FROM_ALLand CI builds onlysamples/baremetal_riscv64/all, so it does not affect other Generic RISCV builds.Also fixes 4
<ctype.h>calls to passunsigned char, as required by the API and exposed by the GCC/newlib build.Assisted-by: Claude Code