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Request IEEE fp32 division for SYCL kernels - #752
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The SYCL compiler defaults to a fast floating-point model in which fp32 division is allowed several ULP of error and `a / b` is lowered to `a * rcp(b)`. Kernels built this way return results that differ from the eager PyTorch ones in the last bit, which breaks kernel tests that compare against PyTorch exactly. Add -foffload-fp32-prec-div and -foffload-fp32-prec-sqrt, matching how PyTorch builds its own XPU kernels in torch-xpu-ops. These affect the offload backend and only take effect when passed to both the device compile and the device link step, so per-kernel `sycl-flags` in build.toml cannot substitute for them. Verified with the activation kernel on Intel Arc Pro B60: its silu_and_mul and mul_and_silu operators go from 42 failures to a fully passing suite, with no change in measured throughput.
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Implement the eleven activation operators in SYCL and register them under the XPU dispatch key, so existing callers work unchanged on Intel GPUs. Previously the kernel declared only cuda, rocm, metal and cpu, and could not be loaded on XPU at all. Gated operators map one work-group to one token; element-wise operators use a flat grid-stride loop. Both use 128-bit vectorized accesses with a runtime alignment check and a scalar fallback, which is what keeps the element-wise operators on par with eager PyTorch, whose TensorIterator already vectorizes. Parameterize tests/kernels/test_activation.py over the available accelerator rather than hard-coding CUDA, so the existing suite runs unmodified on XPU. It passes in full on Intel Arc Pro B60 with torch 2.13.0+xpu, including the gated operators that are compared against eager PyTorch with zero tolerance. Add two cases to the same file for shapes and alignments that force the scalar path, and for empty inputs. Requires huggingface/kernels#752, which makes kernel-builder request IEEE correctly rounded fp32 division for SYCL kernels; without it silu_and_mul and mul_and_silu differ from eager PyTorch by one ULP.
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Summary
Adds
-foffload-fp32-prec-divand-foffload-fp32-prec-sqrtto the SYCL buildflags, matching how PyTorch builds its own XPU kernels in
torch-xpu-ops.Without them the compiler defaults to a fast floating-point model in which fp32
division is allowed several ULP of error and
a / bis lowered toa * rcp(b).Kernels built this way return results that differ from the eager PyTorch ones in
the last bit, which breaks kernel tests that compare against PyTorch exactly.
These flags affect the offload backend and only take effect when passed to both
the device compile and the device link step, so the per-kernel
sycl-flagsinbuild.tomlcannot substitute for them. Applied to thetorchandtvm_ffipreambles alike.
Validation
Verified with
kernels-community/activationon Intel Arc Pro B60 withtorch 2.13.0+xpuand oneAPI 2026.0. Itssilu_and_mulandmul_and_siluoperators go from 42 failures to a fully passing suite (396 cases), with no
change in measured throughput.