T. Reimann, G. Posser, G. Flach, M. Johann and R. Reis, "Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing," 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, 2013, pp. 2549-2552, doi: 10.1109/ISCAS.2013.6572398.
Contest http://www.ispd.cc/contests/12/ispd2012_contest.html
G. Flach, T. Reimann, G. Posser, M. Johann and R. Reis, "Effective Method for Simultaneous Gate Sizing and Vth Assignment Using Lagrangian Relaxation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 4, pp. 546-557, April 2014, doi: 10.1109/TCAD.2014.2305847.
Contest http://www.ispd.cc/contests/13/ispd2013_contest.html