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firrtl-interpreter internal structure

Status: Open.

#148 In freechipsproject/firrtl-interpreter;

· kai413629305 opened on Mar 2, 2019

Bug in handling and() PrimOp with sign extension

bug

Status: Open.

#145 In freechipsproject/firrtl-interpreter;

· chick opened on Jan 14, 2019

How to silence log output during evaluateCircuit

Status: Open.

#141 In freechipsproject/firrtl-interpreter;

· nhynes opened on Dec 4, 2018

"exception Expression key dcache.wen already in stack" when loading riscv-mini's Tile.fir

Status: Open.

#127 In freechipsproject/firrtl-interpreter;

· taomiao opened on Mar 29, 2018

Interpreter's reset behavior does not match verilator backend.

Status: Open.

#118 In freechipsproject/firrtl-interpreter;

· chick opened on Feb 27, 2018

Interpreter should do stronger tests for legal input values

enhancement

Status: Open.

#116 In freechipsproject/firrtl-interpreter;

· chick opened on Feb 27, 2018

Init behavior between interpreter and verilator simulations is different.

bug

enhancement

question

Status: Open.

#110 In freechipsproject/firrtl-interpreter;

· chick opened on Feb 5, 2018

Nobody expects the CombLoopException

Status: Open.

#78 In freechipsproject/firrtl-interpreter;

· ucbjrl opened on Mar 24, 2017

Peek on internal Vec or elements of Seq?

Status: Open.

#43 In freechipsproject/firrtl-interpreter;

· shunshou opened on Oct 21, 2016

Better instrumentation and rendering of that instrumentation

enhancement

Status: Open.

#17 In freechipsproject/firrtl-interpreter;

· chick opened on Aug 4, 2016

·  

Performance Enhancements

Consider using concrete values for indices to memory

enhancement

Status: Open.

#11 In freechipsproject/firrtl-interpreter;

· chick opened on Jul 20, 2016