[XPU] Sync klx d116bdf4 cluster/Python + P-TLE raw frontend (tle.raw) - #1124
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[XPU] Sync klx d116bdf4 cluster/Python + P-TLE raw frontend (tle.raw)#1124dongjibin1996 wants to merge 17 commits into
dongjibin1996 wants to merge 17 commits into
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Import Scalar/Tile/Vectorizability analysis and the new XPU-only passes (Normalize, AsyncLoadSchedule, TLELegalize, LoopInvariantStaging, LegalizeExternEW). Add stage_sm / load_scalar_indexed ops plus GM2SM lowering. Preserve handwritten OffsetAnalysis attrs and keep budget-tiling / loop-invariant-staging off by default. Source: baidu/xpu/triton 6848085b..5a664566. SDNN/.a artifacts are not included.
The C++ binding now requires vrf_budget/budget_tiling/pin_unroll_num. Keep budget tiling off and pin_unroll_num=-1 so vector-add stays on the legacy unroll path.
Merge OffsetAnalysis GetNumPrograms/remsi/handwritten recovery, Scan loop-carry lowering, CoreTiling TypeSwitch getChain, UnrollControl budget model, and LM-only DMA mfence. Drop Pack/Unpack and GetEnv whitelist usage so FlagTree still compiles. P800 vector-add stays max_abs_err=0.0. SDNN artifacts are harvested but not installed.
Extend add_xpu_sdnn_object(TritonSDNNTransforms) to the full internal source list (34 objects). Prebuilt .o files stay gitignored and are installed from the rebuilt artifact dir.
5a664566 TritonSDNNToLLVM.cpp.o needs translateLLVMIRToModule. Keep the dependency on the XPU SDNN target, not the main tree.
Pass load_tile_size into convert-triton-to-tritonsdnn and wire the new SDNN transform passes so mm kernels can compile against the rebuilt objects.
Point xpu.py at the 5a664566 SDNN package. The tarball includes the CombineBefore getenv fix, the v0.3.6.6.0 translation ABI object, and the 28-member libTritonSharedForXPU.a.
Guard XPU ir.cc printers and enable_debug with TRITON_CONCEAL_IR so MLIR_ENABLE_DUMP emits no per-pass IR. Define the macro from third_party/xpu/CMakeLists.txt for XPU Release builds only.
FlagTree default build type is TritonRelBuildWithAsserts, which does not inherit CMAKE_CXX_FLAGS_RELEASE. Define the macro for that config and all non-Debug XPU builds so MLIR_ENABLE_DUMP stays off.
ir.cc is compiled by the top-level triton target, so directory flags in third_party/xpu never reached it. Defer target_compile_definitions onto triton after it is created.
Rebuild XPUToIRTranslationForSDNN.o against llvm_trust from internal 5a664566, and refresh libdevice-xpu3s.bc / liblaunch.a from the same tip. P800 vector-add and fp16 mm stay max_abs_err=0.0.
dongjibin1996
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September 7, 2026 09:43
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Sync the klx d116bdf4 cluster + Python surface into FlagTree and land the tle.raw Python frontend as a vendored XPU overlay (main tree untouched). Cluster sources: - tiling rework (TileAnalysis/TileDecision/VectorizabilityAnalysis, TileDecidePass, UnrollControl, Vectorize rewrite) - vectorized-op fixes, discrete wrap fix - tle.raw C++ (RawOpToLLVM / MaterializeDeferredRaw / TLECoreTiling) - KTC-38 wrapped-index sampling Python vendored gaps (P1): - crash-recovery, default_dot_input_precision, select arch gate, refine_options_after_ttir, bessel j0/j1/y0/y1 SDNN objects: - consume prebuilt v0.3.6.8.0 (object-list prune, getStaticUpperBound vendoring, GetEnv whitelist alignment) - strip debug info from the SDNN package (575MB -> 4.7MB) tle.raw frontend (headline): - gluon_ir.cc: + create_xpu_raw / create_xpu_raw_deferred - Python overlay third_party/xpu/python/triton/experimental/tle/: tle.raw (dialect/call, source_store, cache_key, deferred materialization), tle.gpu, and dsa/pipe stubs - code_generator.py / jit.py / backend/compiler.py / xpu.py plumbing - tle.gpu C++ sync: isTLE pass option + TLE conversion behavior + 10 TLE lowering patterns + type-converter additions Testing: - pytest third_party/xpu/test/tle_raw: 29 passed (on-device P800) - P800 e2e: deferred/eager tle.raw vector-add max_abs_err=0.0; is_sdnn=True rejected with explanation; cross-process payload cache-key invalidation verified - regression: vector-add 0.0; KTC-39 int8->f32 dot 4096/4096 err=0; KTC-38 repeat_interleave 0/11848704 wrong Notes: - SDNN path (sdnn.raw) and tle.dsa/tle.pipe are not available in the XPU build: FlagTree consumes only prebuilt TritonSDNN objects, no IR headers - tle.gpu DMA copy has a known correctness gap on P800 (recorded, not fixed here); the bindings/lowering themselves are complete
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Summary
Sync the klx
d116bdf4cluster + Python surface into FlagTree and land thetle.rawPython frontend as a vendored XPU overlay (main tree untouched).Five stacked commits:
77a0666— cluster sources: tiling rework, vectorized-op fixes,tle.rawC++ (RawOpToLLVM / MaterializeDeferredRaw / TLECoreTiling),KTC-38 wrapped-index sampling.
8edb2ab— P1 Python vendored gaps: crash-recovery, dot precision,selectarch gate,refine_options_after_ttir, bessel.2aff696— Consume SDNN prebuilt objects v0.3.6.8.0: object-list prune,getStaticUpperBoundvendoring, GetEnv whitelist alignment.f0c54dd— Strip debug info from the SDNN package (575MB → 4.7MB).8c9c4ce— P-TLE raw frontend (headline):gluon_ir.cc: +create_xpu_raw/create_xpu_raw_deferred.third_party/xpu/python/triton/experimental/tle/:tle.raw(dialect/call, source_store, cache_key, deferred materialization),tle.gpu, anddsa/pipestubs.code_generator.py/jit.py/backend/compiler.py/xpu.pyplumbing.tle.gpuC++ sync:isTLEpass option + TLE conversion behavior +10 TLE lowering patterns + type-converter additions.
Testing
pytest third_party/xpu/test/tle_raw: 29 passed (on-device P800).tle.rawvector-addmax_abs_err=0.0;is_sdnn=Truerejected with explanation; cross-process payload cache-keyinvalidation verified.
0.0; KTC-39 int8→f32 dot4096/4096 err=0;KTC-38 repeat_interleave
0/11848704wrong.Notes
sdnn.raw) andtle.dsa/tle.pipeare not available in the XPUbuild: FlagTree consumes only prebuilt TritonSDNN objects, no IR headers.
tle.gpuDMA copy has a known correctness gap on P800 (recorded, not fixedhere); the bindings/lowering themselves are complete.