Add SVE2 DescrIntDecode16f optimization

[ermig1979]

Summary

• Add SVE2 DescrIntDecode16f decode kernels for descriptor depths 4 through 8.
• Wire the SVE2 descriptor context and auto-test coverage for DescrIntDecode16f.
• Document the optimization in release 7.2.163 notes.
• Fix SVE half-lane packing so converted fp16 values are stored contiguously.

Testing

• git diff --check
• cmake ./prj/cmake -B build -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_COMPILER=g++ -DCMAKE_C_COMPILER=gcc -DSIMD_TOOLCHAIN="g++" -DSIMD_TARGET="" -DSIMD_AVX512VNNI=ON -DSIMD_AMXBF16=ON -DSIMD_TEST_FLAGS="-march=native" -DSIMD_SHARED=ON && cmake --build build --parallel$(nproc)
• cmake --build build --parallel$(nproc)
• export LD_LIBRARY_PATH="$(pwd)/build:$LD_LIBRARY_PATH" && ./build/Test "-r=." -fi=DescrIntDecode16f -tt=1 -ts=1
• aarch64-linux-gnu-g++ -std=c++11 -fsyntax-only -march=armv9-a+sve2 -msve-vector-bits=scalable -I src src/Simd/SimdSve2DescrIntDec.cpp
• aarch64-linux-gnu-g++ -std=c++11 -fsyntax-only -march=armv9-a+sve2 -msve-vector-bits=scalable -I src src/Simd/SimdSve2DescrInt.cpp src/Test/TestDescrInt.cpp
• aarch64-linux-gnu-g++ -std=c++11 -O2 -S -march=armv9-a+sve2 -msve-vector-bits=scalable -I src src/Simd/SimdSve2DescrIntDec.cpp -o /tmp/SimdSve2DescrIntDec_fixed.s
• Verified generated SVE2 assembly contains fcvt, uzp1, and st1h in Decode16f kernels.