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Add a data structure for memory conf reading and writing - #1041

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jwright6323:mem_conf_pr
Mar 7, 2019
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Add a data structure for memory conf reading and writing#1041
mergify[bot] merged 2 commits into
chipsalliance:masterfrom
jwright6323:mem_conf_pr

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@jwright6323

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This provides a data structure wrapper around the existing memory conf format which contains both reading and writing methods, making it easier to write code that needs to read the format. This should produce identical .conf files to the existing code, so it should be fully backward-compatible. From ucb-bar/barstools#35

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jwright6323 requested a review from a team as a code owner February 28, 2019 05:54
Comment thread src/main/scala/firrtl/passes/memlib/MemConf.scala

def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s)

def fromString(s: String): Seq[MemPort] = {

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Some scaladoc may be useful here; it appears that s is meant to be a comma-delimited list of port types?

Comment thread src/main/scala/firrtl/passes/memlib/MemConf.scala Outdated

val regex = raw"\s*name\s+(\w+)\s+depth\s+(\d+)\s+width\s+(\d+)\s+ports\s+([^\s]+)\s+(?:mask_gran\s+(\d+))?\s*".r

def fromString(s: String): Seq[MemConf] = {

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Scaladoc indicating that this takes in a string containing multiple lines delimited by \n?

@azidar

azidar commented Feb 28, 2019

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Do you think it would be difficult to add a test of this memory configuration stuff?

@jwright6323

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It shouldn't be too hard. I will add some.

This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.
…of a Seq[MemPort] which is a bit less fragile.
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@azidar Done. Let me know if you want anything else.

@azidar azidar added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Mar 7, 2019
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mergify Bot merged commit a97a81b into chipsalliance:master Mar 7, 2019
albertchen-sifive pushed a commit to albertchen-sifive/firrtl that referenced this pull request Mar 18, 2019
…ce#1041)

* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.

* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
ucbjrl pushed a commit that referenced this pull request Mar 26, 2019
* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.

* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
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3 participants