Issues

• How to program both of FPGA bit file and SW binary code into SPI serial flash ?

  chipsalliance/VeeRwolf#79 · Filter by author kidonglee opened on Aug 25, 2025

• VeeRwolf build issue

  chipsalliance/VeeRwolf#78 · Filter by author sabari-vvdn opened on Jun 24, 2025

• Error in Build of Predefined examples of Zephyr

  chipsalliance/VeeRwolf#69 · Filter by author ayusdixit opened on Jan 31, 2024
  2

• May I ask how to generate the build. h file used for FPGA project？

  chipsalliance/VeeRwolf#68 · Filter by author yaanng2022 opened on Nov 27, 2023

• Assertion error when running fusesoc simulation

  chipsalliance/VeeRwolf#67 · Filter by author MoonisAmir10 opened on Aug 29, 2023
  6

• Error when building Zephyr example

  chipsalliance/VeeRwolf#63 · Filter by author aleksaj-vtool opened on Jan 30, 2023
  3

• Read access stops when read/write access is repeated

  chipsalliance/VeeRwolf#59 · Filter by author yafuru0 opened on Dec 26, 2022
  2

• Tested/Implemented on other cores

  chipsalliance/VeeRwolf#58 · Filter by author geoalx opened on Dec 3, 2022

• axi/wb bus cycle times

  chipsalliance/VeeRwolf#55 · Filter by author jamesbbecker opened on Jun 27, 2022
  7

• fusesoc run --target=basys3 with vivado 2021.2

  chipsalliance/VeeRwolf#51 · Filter by author kendallgreen opened on Nov 16, 2021
  5

• [Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

  chipsalliance/VeeRwolf#46 · Filter by author mablinov opened on Oct 13, 2021
  3

• ERROR: [Labtools 27-3165] End of startup status: LOW when [ run --target=nexys_a7 --flag=cpu_el2 swervolf]

  chipsalliance/VeeRwolf#43 · Filter by author nicolast0604 opened on Sep 23, 2021

• fusesoc run --target=sim swervolf with Verilator=3.918

  chipsalliance/VeeRwolf#40 · Filter by author nicolast0604 opened on Jul 22, 2021
  2

• fusesoc run --target=nexys_a7 swervolf with Vivado 2020.1

  chipsalliance/VeeRwolf#39 · Filter by author nicolast0604 opened on Jul 16, 2021
  2

• Do you have any plan to support SweRV-EH2.

  chipsalliance/VeeRwolf#37 · Filter by author nicolast0604 opened on Jul 16, 2021
  2

• Fusesoc Simulation Error

  chipsalliance/VeeRwolf#31 · Filter by author mhamzaali opened on Dec 31, 2020
  1

• Swerv configuration & Swervolf

  chipsalliance/VeeRwolf#30 · Filter by author agrobman opened on Dec 9, 2020

• bscan_tap module - how does it work?

  chipsalliance/VeeRwolf#29 · Filter by author agrobman opened on Dec 5, 2020
  21

• debugging is not working !!!

  chipsalliance/VeeRwolf#26 · Filter by author kidonglee opened on Oct 21, 2020
  12

• verilator + openocd + gdb simulation issue

  chipsalliance/VeeRwolf#25 · Filter by author kidonglee opened on Oct 21, 2020

• Unsupported board in build Zephyr applications

  chipsalliance/VeeRwolf#21 · Filter by author cst-kirank opened on Sep 14, 2020
  6

• Zephyr with adxl362 fails to compile

  chipsalliance/VeeRwolf#14 · Filter by author ddandare opened on May 29, 2020
  1