Issues

• register file example

  cfelton/rhea#61 · Filter by author hashhsah opened on Feb 8, 2019

• spi_slave_fifo_async

  cfelton/rhea#59 · Filter by author mngr0 opened on Sep 30, 2018

• sdram controller

  cfelton/rhea#58 · Filter by author hstarmans opened on Jan 11, 2017
  1

• [enhancement] Provide board definition and blinky example for Red Pitaya

  cfelton/rhea#57 · Filter by author sanojb opened on Dec 21, 2016
  1

• instructions: xula_blinky_host.py on raspberry pi 3B [solved]

  cfelton/rhea#56 · Filter by author hstarmans opened on Nov 17, 2016
  7

• Support Diligent Adept's 'djtgcfg' utility for flow.program() on applicable Diligent boards

  cfelton/rhea#55 · Filter by author NickShaffner opened on Aug 20, 2016
  1

• Symbol 'MMCME2_BASE' is not supported in target 'spartan6'.

  enhancement
  cfelton/rhea#53 · Filter by author NickShaffner opened on Aug 14, 2016 · 0.1
  3

• ClockManagement's 'enable' parameter is not implemented on Xilinx parts

  enhancement
  cfelton/rhea#51 · Filter by author NickShaffner opened on Aug 14, 2016 · 0.1
  2

  

• Would be nice if flow.run() provided board information to the top module for things like ClockManagement

  question
  cfelton/rhea#47 · Filter by author NickShaffner opened on Aug 11, 2016
  2

• [enhancement] create a skipif synthesis tool not available

  enhancement
  cfelton/rhea#45 · Filter by author cfelton opened on Aug 11, 2016

• vga: use the timing parameter class vs. function

  enhancement
  cfelton/rhea#35 · Filter by author cfelton opened on Jul 30, 2016 · 0.1
  

• travis-ci build matrix

  bughelp wanted
  cfelton/rhea#29 · Filter by author cfelton opened on Jun 19, 2016 · 0.1
  

• Add a digilent basys3 board definition

  enhancementhelp wanted
  cfelton/rhea#23 · Filter by author cfelton opened on Mar 30, 2016 · 0.1

• fix test_emesh_fifo test

  bug
  cfelton/rhea#16 · Filter by author cfelton opened on Mar 12, 2016 · 0.2