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Logic-Gates-in-Verilog-
Logic-Gates-in-Verilog- PublicVerilog Code and Testbench for implementation of all basic digital logic gates using Gate, Dataflow, Behavioral Level Modelling.
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Half-Adder-and-Half-Subtractor-in-Verilog-
Half-Adder-and-Half-Subtractor-in-Verilog- PublicVerilog implementation and testbench for Half Adder and Half Subtractor using multiple modeling styles.
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Full-Adder-Full-Subtractor-Verilog
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4-1_MUX-Verilog
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1-4_DEMUX-Verilog
1-4_DEMUX-Verilog PublicVerilog Code and Testbench for implementation of 1:4 Demultiplexer using multiple modeling styles.
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4-Bit-Ripple-Carry-Adder
4-Bit-Ripple-Carry-Adder PublicDesign and simulation of 4 Bit Ripple Carry Adder using Verilog HDL with full adder instantiation modules and a verified testbench
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