[laudney]

For whole shared-expert outputs (TP1, or TP2 with dense splitting disabled), this PR writes the FP32 down result directly into slot 10 instead of writing a contiguous result and scattering it. The standalone-on-PR1 4218-row measurement is 0.867 → 0.406 ms (2.13x); its served change is small. Default TP2 split output keeps PR2's gather/full-input projection/raw-copy path and does not use the direct-slot kernel.

Refs #1754. Depends on PR2 #1784, which follows frozen PR1 #1771 (6d2fc036). One operator commit above #1784; head 64acba2f8. Incremental diff.

What

• Add four strided BF16-weight/FP32-output qmmf entries for whole shared down: width 640, output width 2560, 11 slots, shared slot 10. The whole-output path keeps the shared expert on rank 0. Routed slots and the ordered MoE combination keep their bytes.
• Require a whole output before selecting direct slot output. Default split TP2 retains its BF16 intermediate gather, two interleave copies, full-K640 down projection and raw FP32 output-column copy. A half-output projection must never select the strided kernel.
• Use planFor to honor pinned K slices. Preserve qmmf arithmetic and K-slice order; change the whole-output address. Keep the contiguous fallback and the 1536-row prompt default.
• With dependent BF16 Flash Next BF16 prompts: larger CUDA tiles with identical output bytes #1846/Flash Next BF16 prompts: reduce shared staging with K32 loads #1848 loaded, direct output yields to eligible 128-row prompt projection plus scatter at >=512 rows. Forced-direct fixtures retain kernel coverage when automatic selection yields. The gains are not additive.

Gate (GB10, sm_121, CUDA 13.0.88)

Ash's latest landing order is PR1, then PR2, then #1792. The issue requirements also require one kernel replacement per PR, matching bytes, contract records and a planted control. This branch follows #1784; CI is checked separately on its current head.

• Replacement bytes: the qualified moetile run passes eight row counts, five repeats, unchanged inputs and guards around every slot. moetile-contract gates 1–4: 4 pass, 0 fail; 1 planted control red, 0 missed, against contiguous down plus scatter.
• Code generation/resources: CUDA/qmmf blobs retain their qualified images: 400 old qmmf entries unchanged, 20 shared entries added across sm_80/86/89/120/121. CUDA 13.0 records match loaded sm_121 entries: 40/38/56/72 registers, zero user static shared bytes and 128-thread bounds.
• Current ordered host gate: 324/324 pass. This includes the explicitly discovered test-flashnext-compose-host target, 36/36, plus shared/runtime tests. The composition fixture requires a unique BF16 gather, its two immediate interleave copies, full-K640 down and the raw FP32 output copy, and refuses strided half outputs. It permits the valid gate/up reducers at 64 rows and initializes the mock mixed input.
• Windows fixture compatibility: the four POSIX socket-pair tests now explicitly skip on Windows. The full FlashNext test module cross-compiles for x86_64-windows-gnu; Windows execution remains a separate CI check. The corrected shared target passes 36/36 on Linux, and the full final series passes 228/228 again. Runtime and CUDA code are unchanged.
• Full-series fixture regression: the unfiltered FlashNext host module passes 228/228 at two seeds. A planted bad guard that enables direct half-output stores is red (35 pass, 1 fail), preserving the witness.
• Native/consumer scope: the standalone-on-PR1 native suite passes six draft/plain cases, mixed/cancel lifecycle, cold 2k/8k/32k/64k, four concurrent 8k requests and non-drafting cache reuse. Earlier qualified CUDA-runner/ModelOpt-startup compilation passed. The ordered K32 tip now passes 15/15 consumer build steps (tf-cuda-test fast native and tensorfold-native safe native). These use inert images for compilation only; the binaries were not executed.

The full ordered series has the qualified combined runtime and CUDA source; the qualified-series branch changes only two host-test files relative to 64d499e8f for discovery, launch assertions, mock initialization and Windows fixture skips. The earlier TP1 and TP2 split-on, plus TP2 split-off native receipts therefore remain runtime-equivalent; they are not new GPU runs on this head. PR2 #1784 records that composition scope. The canonical combined qmmf image preserves the 450-entry qualified union.

Other physical SMs and later compilers remain unrun. This is not a clean global CUDA-suite claim: the related full contract had 546 numerical passes, 349 red controls, six known findings and 181 inherited resource issues (exit 1). This operator's four loaded entries match their records.

Numbers

These measurements use the standalone shared operator on PR1, before the PR2-first composition:

Scope	Before	Direct output	Meaning
Shared down, 4218 rows	0.867 ms including scatter	0.406 ms	2.13x operator gain
Isolated cold 32k median TTFT	22.251 s	22.129 s	0.55% lower

The operator measurement is above the unchanged 1536-row default. It does not establish default TP2 or full-series speedup; default TP2 takes PR2's full-input column path.

Overlap

Order: #1771 → #1784 → shared #1792 → BF16 #1846 → K32 #1848. HC normalization #1847 and HC mix #1849 form an independent stack on PR2. GDN prefetch and NVFP4 K32-down stay local and off after losses or no consistent default-chunk gain.

#1764 overlaps the BF16/HC implementations. Direct slot output is distinct from its contiguous shared output plus scatter. Choose one canonical BF16 dispatcher before combining the later alternatives, preserving pinned full-input slices and the split-output guard.

[ashhart]

Thanks @laudney. Our light gate's only finding on this stack (#1771 + #1784 + this) is the 600-line rule: zig/src/native/cuda.zig reaches 607 on current main (main has 594). The new test "the CUDA server serves --tp, and Flash Next's two ranks pass family admission" accounts for most of it, so moving that test beside the refusals' own tests, or into a small test file, should bring it back under. Everything else in the gate passes, and the stack's served cells are running on a GB10 now against main, with the Flash Next FP4 checkpoint, base/new/new/base.

[laudney]

Thanks @ashhart. Fixed in #1771 (9c7c77262, on top, no force-push): Fish's and Qwen4's --tp refusal moved into refusals.backend(), which open() already calls before either family opens, and the test now sits beside the refusals' own rank tests in cuda_refusal.zig. open() reads as on main, and zig/src/native/cuda.zig is 598 lines with current main merged in (42eb861a4).

Following your plan on #1754, this pull request will be replaced by one pull request per kernel once #1771 lands.