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Thanks @gilby. This meets the gate we posted. The item tile is in the routed byte-equality sweep against the matrix, GEMM and K-parallel tiles, served tokens are unchanged on both checkpoints, the |
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An update after #1663 landed and with #1651's 4,096-row chunks in view: the 64-row tile now runs only for prompt chunks of at most 1,024 rows ( The pairs-per-item bound reads the plan's item capacity as the launch passes it (
On the rebased head (main So the new |
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Thanks @gilby. Our review says this lands: 34356b1 caps the 64-row routed tile at prompt chunks of 1,024 rows, the tile is byte-equal to the 128-row one at every routed cut, and other GPUs are unchanged. But it conflicts with main now in |
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Thanks @ashhart. Rebased onto On the rebased head, gfx1151: With |
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Thanks @gilby: the push is a clean rebase of what we cleared (the 64-row item tile, gfx1151's table, the 1,024-row chunk cap, contract records and sweep), and other GPUs are unchanged. It's in the landing queue. |
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Rebased onto current main (cfcbecb), keeping your changelog commit as it was. The only conflict was the CHANGELOG, where main added entries beside it; both are kept. The three code commits applied unchanged. Receipts on the rebased head (32dff8d), one Strix Halo iGPU (gfx1151), ROCm 7.1 hipcc, zig 0.17.0:
Not run: gfx1030, gfx1100 and gfx1201 hardware, and any other family. |
A routed prompt plan with hundreds of experts gives each item a few rows to a few dozen, but the routed matrix-core tile is 128 rows, so most of its waves skip their WMMA while still staging weights. A 64-row tile over all waves keeps the 128-row tile's staging and fold, so its rows are byte-identical. gfx1151 gets its own table: gfx1100's rows plus the new tile for routed plans of up to 12 pairs an item, using the pairs-per-item bound from ashhart#1607. Fixes ashhart#1601
The pairs-per-item bound reads the plan's item capacity, which grows with the pairs, so it admitted the 64-row tile at every chunk size. With the matrix tile's loop free of selects (ashhart#1663) the 128-row tile is faster once an expert holds the rows of a longer chunk, so the 64-row tile now also needs a chunk of at most 1,024 rows.
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What this changes
A routed prompt matrix-core tile of 64 rows an item (
affine_wmma_item<BITS, 4>, all 8 waves across the 128 columns, the 128-row tile's staging and fold unchanged, so rows are byte-identical), selected through a newgfx1151.zon(gfx1100's rows plusmlx.routed.prefill.item64at cost 9 for routed plans of up to 12 pairs an item, using #1607's pairs-per-item bound). Fixes #1601.Receipt
f350cd3e(with HIP: bound the routed prompt's K-parallel tile by pairs per item, and give it gfx1201's short prompts #1607) plus this change,tensorfold-native 1.1.8built withzig build native-hip -Dhip-arch=gfx1151, Ubuntu archive HIP 7.1 (clang 21), AMD Ryzen AI MAX+ 395 with Radeon 8060Sgfx1151(128 GB unified memory). CheckpointsTensorFold/Qwen3.8-Flash-Next-MLX-4bit-MTPrevision2b170fa6and an oMLX oQ4e quantization of Qwen3.8-Flash-Next, MTP 3 drafts,--parallel 1 --context 131072 --prompt-cache-gib 0 --policy prefill_step=4096, main and candidate on the same machine.token_sha256oftools/bench_openai.py,tools/bench_concurrent.pyand bothtools/bench_cache.pyprompts identical to main on both checkpoints;bench_concurrent --alone --serial0 failed, 0 unmeasured, every cell equal.zig build hip-affine-tuneon gfx1151 at Flash Next's served routed plans (512 experts plus the shared one, 11 slots), us, 128-row tile -> 64-row tile: gate/up (n 1280, k 2560) 256 tokens 10,987 -> 9,741, 512 tokens 11,576 -> 9,932, 1,024 tokens 21,215 -> 10,629, 2,048 tokens 25,580 -> 12,303; down (n 2560, k 640) 5,790 -> 3,425, 6,343 -> 3,737, 11,465 -> 4,702, 14,281 -> 6,325. Plans of 1 to 64 tokens also favour it by about 10%. Those plans hold 3.3 to 6.8 pairs an item; a 4,096-token chunk holds about 9, so the bound is 12 (not timed at 4,096 directly; the served runs below use that step).tools/bench_openai.py --tokens 256 --reps 3 --temperatures 0: unchanged (4-bit 50.0 / 43.9 -> 50.2 / 44.1, oQ4e 42.1 / 36.2 -> 42.0 / 36.2 tok/s code / chat; decode takes the stream tiles).tools/bench_cache.py --require-cold --tokens 16on public 7,377- and 29,364-token arrays,ttft_sof the cold request after the warm-up: 4-bit 20.72 -> 19.90 s and 91.79 -> 88.48 s (-4.0% / -3.6%); oQ4e 22.42 -> 21.40 s and 95.37 -> 92.40 s (-4.5% / -3.1%). One run per cell. The routed products are a larger share of prompt time once the sparse attention is faster (HIP Flash Next: WMMA sparse attention for prompt chunks on gfx11 #1597), so the gain should grow with it.zig build hip-kernel-contracton gfx1151:SUMMARY gfx1151 51 kernels: 51 pass gates 1-4, 0 fail, 0 known findings; 5 controls: 5 red as planted, 0 missed; 126 limit problems(main: 50 kernels, the same 126 live-versus-recorded register differences for existing kernels under this machine's compiler); the new tile's cases (groups 32 and 64): non-finite, repeat, shapes and sums pass, byte-equal to the 128-row tile it replaces; live limits 176 VGPRs and 34,304 LDS bytes as recorded.zig build hip-kernel-test106/106 (the routed prompt byte-equality test now compares the new tile against the matrix, GEMM and K-parallel tiles on every routed prompt cut).zig build test -Dhip=true --summary all468/468 steps, 0 failed.python3 tools/zig/lean_check.py426 on main and change.git diff --checkclean.hip-kernel-contract-limitsstops on this machine's compiler attiles/dot2_tiles.hipfor gfx1100 (branch size exceeds simm16, same on main, see HIP: dot2_tiles.hip fails to compile for gfx1100 with Ubuntu clang 21.1.8 ("branch size exceeds simm16") #1521); the records for gfx1030, gfx1100 and gfx1201 come from compiling the tile for each chip and reading its code object (gfx1030 and gfx1201 get a trapping stub, as they have no gfx11 matrix cores, and never select it). gfx1100 keeps its table unchanged (not measured there). Metal and CUDA.Checklist
"draft": false, a resumed prompt equals a fresh one, and concurrent equals solo.SUMMARYline is in the receipt.