LFM3-1.7B on the XPU backend (Intel GPUs, Iris Xe first) #1666

Goal

Serve LFM3-1.7B (text, MLX affine 4-bit, group 64) on the XPU backend, so the Intel GPU path has a model that fits small machines. The first target is an Iris Xe laptop (Gen12LP, no DPAS, 16 GB shared RAM). Nemotron 3.5 Lightning 30B-A3B, the only model XPU serves today, does not fit there.

Scope

• A new family module families/lfm3/xpu_*.zig:
  • the gated short convolution (conv state per stream);
  • GQA attention with QK norm;
  • the SwiGLU MLP;
  • tied embeddings.
• Kernels:
  • existing kernels are reused where they fit: qmv4, attn and glue;
  • one new OpenCL C kernel for the short convolution, plain sub-group code with no DPAS, so Gen12LP and Xe2 both build it.
• Config and weight names come from lfm3: admit official MLX text and VL checkpoints #1513's families/lfm3. This work stacks on it until it lands.
• Gates:
  • each new kernel against an FP64 host replay;
  • the whole forward against an FP64 reference on fixed prompts;
  • greedy tokens against the CUDA (lfm3: serve LFM3-1.7B on CUDA: NVFP4 and FP8 weight-only, MLX 4-bit (stacked on #1513, #1492 and #1503) #1508) and Metal (lfm3: serve the MLX text decoder on Metal #1514) paths;
  • serve end to end with a chat request.
• Not in scope: vision, drafts, prompt cache, sampling beyond what the XPU lane core already offers.

Order

1. The kernels plus contract checks with synthetic weights, so no checkpoint is needed.
2. The forward on the checkpoint, with the FP64 reference compared layer by layer.
3. Wiring into xpu-native serve and the docs/recipes/xpu-arc.md table, then measuring on Iris Xe and, if someone has one, on Arc.

Related: #1491 (LFM3 on Metal), #1508 (LFM3 on CUDA), #1513 (LFM3 admission).