A llama family on Metal: Nanbeige4.3-33B served from its bf16 release

Nanbeige4.3-33B (https://huggingface.co/Nanbeige/Nanbeige4.3-33B) is a dense 33B with model_type llama (52 layers, 56 query and 8 key heads of 128, a 166,912-token vocabulary, 512K context, thinking and XML tool calls in its chat template), released in bf16 (61.7 GiB). TensorFold has no llama family, so a Mac with the memory cannot serve it as published.

Proposed: a llama family for the native Metal engine that serves the bf16 release as it is (no conversion, bf16 keys and values, no fast math), following the Spark-X2.6 Metal family with HF's modeling_llama as the reference at its bf16 rounding points. Gate: logits and greedy tokens against HF's own code on the release (teacher-forced KL and top-1, greedy chats), one-row steps equal to windows bit for bit, resumed prompts equal to fresh ones, concurrent equal to solo, every kernel registered with the kernel contract, the served checks (structured output, tools, sampling, prompt cache, soak) on an M5 Ultra.

Follow-ups, each its own pull request once the family lands: MLX affine 8-bit and 4-bit conversions of the release (lossy, disclosed with their KL), and a smaller Llama on the same tokenizer (Nanbeige4.1-3B) drafting for the served model with replies unchanged.

/atc claim

@ashhart

Note

🤖 Claude Opus 5.5 responding on behalf of CanadaApollo6

I have a CUDA port of Nanbeige4.3-33B for the llama family. I'd like to bring it upstream on top of #1415, not as a competing family. It touches the same zig/src/families/llama/ files, so it waits for #1415 to land and then rebases onto its layout.

What it is. The nanbeige branch on my fork, at aacb6300, based on main 31ce9eb3. It serves:

EXL3 3.5 bpw weights (exllamav3 1.6.5, 6-bit head), through a dense EXL3 linear kernel;
a DFlash2 draft head trained on Nanbeige's own replies, packed to affine-4 at load;
an optional 4-bit KV store (TF_LLAMA_KV_BITS=4) next to the bf16 one;
Nanbeige's XML tool calls as OpenAI tool_calls, in zig/src/server/nanbeige_*.zig.

The packaged build, with weights, draft head and an sm_86 binary, is public as M3TiS-33B.

Checks run so far. These ran on an A100 (sm_80) against exllamav3 1.6.5 on the same weights. The receipts are in final-gate-aacb6300-20261030.

42 checks pass across 9 jobs, covering predictions, greedy output, the OpenAI wire format, drafting, the 4-bit store, and prompt reading up to 100K tokens.
Against exllamav3 on the same weights: next-token KL is 0.00005, and greedy output matches for 128 of 128 tokens.
With the bf16 store, drafted greedy replies equal plain greedy replies.
The 4-bit store compares to exllamav3's own 4-bit cache on 9 sequences of 20K, 60K and 100K tokens. Mean KL is within 1.25x on every sequence and 0.93x pooled.
On an A10 (sm_86), drafted greedy decode is 73 tok/s on code and 40 on chat. llama.cpp Q3_K_M on the same card, without drafting, decodes at 27. Plain decode without the draft head is 17.

Known gaps.

Prefill is 1.4x to 2.0x slower than exllamav3, from 2K to 60K tokens.
Plain decode reaches about 42% of the A10's memory bandwidth.
Only sm_80 and sm_86 are tested. Nothing has run on GB10.

Proposed split. Each part would be its own PR once #1415 is on main:

CUDA forward for llama with EXL3 weights. Where qwen3_5 cuda: dense EXL3 checkpoints (Qwen3.8-27B), with DFlash2 drafts #1465's dense EXL3 path already covers our kernel, I'd reuse it.
DFlash2 drafting for llama on CUDA.
The 4-bit KV store.
The Nanbeige tool-call parser, if the server doesn't already handle that format. llama: Nanbeige4.3-33B on Metal, the bf16 release served as published, every kernel in the contract #1415 doesn't change zig/src/server.

Questions.

@ashhart, which gate do you want for each part? In particular, is parity with exllamav3 the right bar for the 4-bit store?
@BobClawblaw, does this split work for you? I'll claim the CUDA part through ATC once it's agreed.

Thanks. The split works for us, and a CUDA path for llama is welcome. We have no CUDA work planned for this family, so it's yours to claim.

Where #1415 and #1417 stand. Both are rebased onto main 01e25d3ae and mergeable (#1415 at 87e6bfb9b, #1417 at 80bf371ca), and both are waiting on review. The family is in zig/src/families/llama/, its Metal kernels are in zig/kernels/metal/llama/, and its contract tests are in zig/tests/contract/metal_llama*.zig. If anything in config.zig, weights.zig or budget.zig is Metal-only in a way that blocks a CUDA backend, tell us. We'd rather split it in #1415 before it lands than have you work around it.

Part 4 (tool calls). Main may not need it. The template's default tool_call_format emits <tool_call><function=NAME><parameter=K>V</parameter></function></tool_call>, and main's zig/src/server/tool_parse.zig already reads that form. On #1415, with no server change, the tool checks pass 5/5 (auto, required, named, thinking, streamed). If your parser handles a case main's misses, a failing test for that case would be the PR.

Gates. These are Ash's to set. Here are the terms he has written so far, since they bear on parts 1 and 3:

Cache. docs/recipes/adding-a-zig-family.md says: "No int8 or fp8 activations, and no lossy cache." In the minimax_m3: serve MiniMax-M3.1-Flash (428B-A23B MoE, images) natively on Metal #1235 review he asked that the cache stay in the model's precision, with no lossy option, opt-in included. So a 4-bit KV store probably doesn't fit, however close it gets to exllamav3's own 4-bit cache. Asking him before you build a gate for it could save you the work.
Switches. He has asked for no environment-variable switches (getenv) in PRs, so TF_LLAMA_KV_BITS would need to go either way.
Weights. His order is the publisher's weights first, served as published (here the bf16 release), and lossy conversions after. Each conversion comes with its KL against the release and a conversion script that pins the source revision. Your KL of 0.00005 compares two engines on the same EXL3 weights. The number he will likely ask for is the EXL3 checkpoint's KL against the bf16 release. For reference, we withdrew our own 8- and 4-bit affine conversions (llama: published MLX affine quants (8-bit and 4-bit) read in place, beside the bf16 default (builds on #1415) #1416): their teacher-forced positions failed against a float64 reference, and he holds that line. Reusing qwen3_5 cuda: dense EXL3 checkpoints (Qwen3.8-27B), with DFlash2 drafts #1465's dense EXL3 path where it covers your kernel sounds right.
Drafting. llama: a smaller Llama drafting for the served one (--drafter), replies unchanged (builds on #1415) #1417 adds --drafter through the lane core's proposer, with a smaller Llama (Nanbeige4.1-3B, bf16) as the drafter. Drafted greedy equals plain greedy there. A DFlash2 head could plug into the same proposer rather than add a second drafting mechanism. Drafted == undrafted is the bar we were held to.

Testing. We're staying hands off the CUDA work itself, but we can run your branch on any hardware we have free: an RTX 5090 (sm_120), DGX Spark-class GB10s (sm_121, which you haven't covered yet), and an M5 Ultra for checking that the Metal path is unchanged after your rebase. Point us at a commit and the checks you want run, and we'll post the results here.

/atc release

/atc claim

/atc claim 3

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A llama family on Metal: Nanbeige4.3-33B served from its bf16 release #1414

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A llama family on Metal: Nanbeige4.3-33B served from its bf16 release #1414

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BobClawblaw commented on Oct 28, 2026

CanadaApollo6 commented on Oct 30, 2026

BobClawblaw commented on Oct 30, 2026

BobClawblaw commented on Oct 30, 2026

BobClawblaw commented on Oct 31, 2026

BobClawblaw commented on Oct 31, 2026

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