aiur: correct memory circuit width in statistics (size + 7)#501
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arthurpaulino wants to merge 1 commit into
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aiur: correct memory circuit width in statistics (size + 7)#501arthurpaulino wants to merge 1 commit into
arthurpaulino wants to merge 1 commit into
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Mirrors crates/aiur/src/memory.rs: multiplicity + selector + pointer + size value columns, plus one lookup -> 2*(1+1) stage-2 columns. The old size + 11 over-counted every memory circuit by 4. Re-pin all 56 kernel-check FFT costs from a full `lake test -- --ignored ixvm` run (all green); every pin drops since the reported memory-circuit cost deflates. Actual proving cost is unchanged.
arthurpaulino
enabled auto-merge (squash)
July 18, 2026 00:41
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Mirrors crates/aiur/src/memory.rs: multiplicity + selector + pointer + size value columns, plus one lookup -> 2*(1+1) stage-2 columns. The old size + 11 over-counted every memory circuit by 4.
Re-pin all 56 kernel-check FFT costs from a full
lake test -- --ignored ixvmrun (all green); every pin drops since the reported memory-circuit cost deflates. Actual proving cost is unchanged.Closes #496