[JoelRamireddy]

Fixes #354

In the CMSIS device headers for 10 RA chips, GTCR.TPCS (Timer Prescaler Select) is defined at the wrong bit position with the wrong width.

Current definition:

#define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) /
#define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /!< TPCS (Bitfield-Mask: 0x0f) */

The RA4M1 User's Manual, section 22.2.12 (General PWM Timer Control Register), shows TPCS[2:0] as a 3-bit field at b26 to b24, with b23 to b19 reserved. The current definition is off by one and 4 bits wide, so the mask also covers reserved bit 23.

Fixed definition:

#define R_GPT0_GTCR_TPCS_Pos (24UL) /*!< TPCS (Bit 24) /
#define R_GPT0_GTCR_TPCS_Msk (0x7000000UL) /!< TPCS (Bitfield-Mask: 0x07) */

This matches the Renesas FSP headers (v6.6.0) for each of these chips.

Devices changed (all had 23 / 0x7800000 before, and now match FSP v6.6.0 with 24 / 0x7000000):

• R7FA2A1AB
• R7FA2E1A9
• R7FA2E2A7
• R7FA2L1AB
• R7FA4M1AB
• R7FA4W1AD
• R7FA6M1AD
• R7FA6M2AF
• R7FA6M3AH
• R7FA6T1AD

Each board under variants/ carries its own copy of the FSP include tree, so the same headers exist in every variant. 10 headers x 7 variants (MINIMA, MUXTO, NANOR4, OPTA_ANALOG, OPTA_DIGITAL, PORTENTA_C33, UNOWIFIR4) = 70 files. Each file gets the same two-line change, 140 lines in total. Nothing else is touched, and the variant trees are not deduplicated.

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