B.Tech ECE · 3rd Year · Vignan's Institute of Information Technology, Visakhapatnam
Building a complete VLSI design portfolio from first principles — logic gates → combinational → sequential → FSMs → 16-bit pipelined RISC processor
I'm a 3rd-year B.Tech ECE student (CGPA: 9.68) specialising in RTL design and digital verification. My primary focus is building a structured, self-directed VLSI portfolio — 8 repositories that form a continuous build from AND gates up to a full 5-stage pipelined RISC processor in Verilog. I also work on embedded systems projects and am preparing for GATE ECE 2027 in parallel.
A single structured build: each repo feeds directly into the next, culminating in a 16-bit pipelined RISC processor on FPGA.
| # | Repository | Status | Contents |
|---|---|---|---|
| 01 | basic-logic-gates | ✅ Complete | AND, OR, NOT, NAND, NOR, XOR, XNOR — with testbenches and GTKWave waveforms |
| 02 | combinational-circuits | ✅ Complete | Adders, MUX, Decoder, Encoder, Comparator, 16-bit ALU — Yosys synthesis + GLS |
| 03 | sequential-circuits | ✅ Complete | Flip-Flops, Registers, Counters, Shift Registers, Synchronous SRAM 256×16 |
| 04 | finite-state-machines | 🔨 In Progress | Moore FSM, Mealy FSM, Traffic Light Controller, 1011 Sequence Detector, UART, SPI, Debounce |
| 05 | 05-alu-16bit | ⏳ Upcoming | SystemVerilog ALU + Formal Assertions + Synthesis |
| 06 | 06-processor-components | ⏳ Upcoming | PC, Control Unit, Register File, Hazard Unit |
| 07 | 07-risc16-pipelined-processor | ⏳ Upcoming | Complete 5-stage pipelined RISC processor |
| 08 | 08-protocols-and-interfaces | ⏳ Upcoming | UART, SPI, AXI4-Lite in SystemVerilog |
All 7 fundamental gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) implemented in Verilog from scratch, each with a dedicated testbench and GTKWave waveform verification against complete truth tables.
Verilog · Icarus Verilog · GTKWave
17 circuits from half-adder to a full 16-bit ALU, including a 16-bit Ripple Carry Adder, Adder-Subtractor, Magnitude Comparator, and priority encoders. Three key modules (Full Adder, 16-bit Adder-Subtractor, 16-bit ALU) synthesised with Yosys and verified via gate-level simulation.
Verilog · Icarus Verilog · GTKWave · Yosys · Graphviz
All major sequential building blocks: D/T/JK/SR flip-flops, 4-bit and 16-bit registers, up/up-down/BCD/Gray code counters, all four shift register modes (SISO/SIPO/PISO/PIPO), and a 256×16 synchronous SRAM — the same SRAM that becomes the data memory stage in the final processor.
Verilog · Icarus Verilog · GTKWave
🔷 04 — Finite State Machines (In Progress)
Moore and Mealy FSMs, Traffic Light Controller, 1011 Sequence Detector, UART Transmitter, UART Receiver, SPI Master, and Debounce Circuit — all in Verilog with simulation-verified waveforms.
Verilog · Icarus Verilog · GTKWave
A Python CLI framework for RTL regression testing: auto-compiles Verilog with iverilog, runs simulations, parses PASS/FAIL results, and generates an HTML dashboard and JSON report. Supports watch mode, tag-based test filtering, Vivado synthesis report parsing, and CI/CD integration. Built with collaborator Sujeet Kona.
Python · Icarus Verilog · watchdog · Vivado
Structured Verilog problem-solving on HDLBits, running in parallel with the 8-repo VLSI portfolio.
Verilog · HDLBits
Real-time environmental and inertial data acquisition with wireless downlink, simulating a CubeSat ground-link scenario. Uses LoRa at 433 MHz for 2km+ range communication. Hardware: ESP32, INA219, BMP280, DHT11, MPU6050, SX1278 LoRa · Skills: Embedded C, SPI, I2C, PCB design
A wearable glove that maps hand gestures to commands using flex sensors and an IMU. Hardware: Flex sensors, IMU, microcontroller · Skills: Signal processing, embedded firmware, hardware prototyping
Hardware Description
Simulation & Synthesis
Embedded Systems
Tooling
- 🔨 Building Repo 4 — Finite State Machines (Moore, Mealy, UART, SPI Master, Debounce)
- 📖 GATE ECE 2027 preparation running in parallel
- 🎯 Target: complete 16-bit pipelined RISC processor by October 2026
Building from AND gate to a 16-bit pipelined RISC processor — one module at a time.