Gap
The simulator has no XFR2VBUS model. Access to IDs 0x60/0x61 (read) and
0x62/0x63 (write), plus 0x64 for the TX_PRU receive path, falls through to
the unknown-XFR zero/discard behavior.
Requested scope
Model the bounded command/data FIFO behavior from AM64x/AM243x TRM SPRUIM2J
section 6.4.6.3.1, Tables 6-106 and 6-107:
- read configuration/status through R18 and address through R19:R20;
- 4/32/64-byte aligned reads, with one command in flight;
- 1/4/32/64-byte writes with the documented register ranges;
- status (
BUSY, command-FIFO and data-FIFO flags) that observes queue state;
- an injected backing-memory interface and deterministic latency so tests can
exercise empty/full paths.
Non-goals for the first PR
No claim of CBASS arbitration or cycle equivalence. Auto-read can be a
separate follow-up once a single bounded read/write transaction is executable.
Acceptance
An ELF/assembly test must demonstrate a completed read, a completed write, and
the failure/blocked path for an empty RX or full command FIFO. Tests must
assert the status bits, not just memory contents.
Gap
The simulator has no XFR2VBUS model. Access to IDs
0x60/0x61(read) and0x62/0x63(write), plus0x64for the TX_PRU receive path, falls through tothe unknown-XFR zero/discard behavior.
Requested scope
Model the bounded command/data FIFO behavior from AM64x/AM243x TRM SPRUIM2J
section 6.4.6.3.1, Tables 6-106 and 6-107:
BUSY, command-FIFO and data-FIFO flags) that observes queue state;exercise empty/full paths.
Non-goals for the first PR
No claim of CBASS arbitration or cycle equivalence. Auto-read can be a
separate follow-up once a single bounded read/write transaction is executable.
Acceptance
An ELF/assembly test must demonstrate a completed read, a completed write, and
the failure/blocked path for an empty RX or full command FIFO. Tests must
assert the status bits, not just memory contents.