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Fix/usb phy clock ungate - #160
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HAL_PCD_SuspendCallback stops the PHY clock (__HAL_PCD_GATE_PHYCLOCK, PCGCCTL.STOPCLK), but nothing ever restarts it: HAL_PCD_ResumeCallback only calls USBD_LL_Resume, and the H7 HAL does not ungate on wakeup or on bus reset. A sensor that goes through a suspend therefore keeps a suspended PHY while the stack still reports CONFIGURED. On the bench this wedges a sensor after a power cycle or a firmware update: it enumerates, the host's first connect gets a pipe error about 1 s after opening it, and from then on every bulk write times out and EP0 requests fail until the module is power-cycled. An SWD dump of a wedged sensor showed the CPU and USB stack healthy, the device configured at the host's address and SOFs arriving, with PCGCCTL = 0x1; the host's requests never reached the firmware. The bare-metal sensor hit it; the one behind the secure bootloader has not, most likely because the bootloader delays USB start past the suspend window. Ungate the PHY clock at the start of the resume callback (as ST's ULPI reference code does) and of the reset callback, since a bus reset can end a suspend without a resume interrupt. Bench, released test app 1.5.2-rc.0, bare-metal 1.8.3-rc.3 on the right sensor: unpatched, 4 wedges in about 14 power cycles and a connect-time pipe error on about half of them; patched, 10 of 10 cycles clean with no pipe errors. Signed-off-by: George Vigelette <george@openwater.cc>
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